US4409674A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Fujitsu Ltd
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Filing: 1980-08-22
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Granted: 1983-10-11
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Expires: 2000-08-22
Abstract
Abstract In a semiconductor memory which is provided with a memory cell array, word lines and bit lines for selecting a desired one of memory cells of the memory cell array and a detector circuit for detecting a read current of the selected memory cell, the detector circuit is composed of a pair of transistors having their bases cross-connected so that a hysteresis characteristic is provided by flowing a current in the transistors, and the current is controlled by a hysteresis control circuit to flow only when all word line potentials monitored by the hysteresis control circuit have become lower than a predetermined value, whereby to remove the influence of a noise in the detection of read information of the selected memory cell.
Inventors
- 👤 Yukio Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:44
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/065; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/416; G11C7/062
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
140 words
A semiconductor memory which is provided with a memory cell array composed of a plurality of memory cells, word lines and bit lines for selecting a desired one of the memory cells, the semiconductor memory comprising: a detector circuit for detecting a read current of the selected memory cell of the memory cell array, said detector circuit including a pair of transistors having their bases cross-connected to provide a hysteresis characteristic which is obtained by applying currents to the transistors, and a hysteresis characteristic control circuit which monitors the potentials of the word lines and effects a flow of current to the pair of transistors for providing the hysteresis characteristic only when all the word line potentials have become lower than a predetermined potential, said detector circuit retaining data read immediately before while being supplied with said flow of current.
Claim 2
Dependent Claim
140 words
A semiconductor memory which is provided with a memory cell array composed of a plurality of memory cells, word lines and bit lines for selecting a desired one of the memory cells, the semiconductor memory comprising: a detector circuit for detecting a read current of the selected memory cell of the memory cell array, said detector circuit including a pair of transistors having their bases cross-connected to provide a hysteresis characteristic which is obtained by applying currents to the transistors, and a hysteresis characteristic control circuit which monitors the potentials of the word lines and effects a flow of current to the pair of transistors for providing the hysteresis characteristic only when all the word line potentials have become lower than a predetermined potential, said detector circuit retaining data read immediately before while being supplied with said flow of current.
Claim 3
Dependent Claim
110 words
A semiconductor memory which is provided with a memory cell array composed of a plurality of memory cells, word lines and bit lines for selecting a desired one of the memory cells, comprising: a detector circuit for detecting a read current of the selected memory cell of said memory cell array; means included as part of said detector circuit for providing hysteresis characteristics thereto so that said detector circuit can retain data read immediately before; and means for monitoring the potentials of said word lines and effecting a flow of current for providing the aforesaid hysteresis characteristics only when all the word line potentials are lower than a predetermined potential.
Claim 4
Dependent Claim
110 words
A semiconductor memory which is provided with a memory cell array composed of a plurality of memory cells, word lines and bit lines for selecting a desired one of the memory cells, comprising: a detector circuit for detecting a read current of the selected memory cell of said memory cell array; means included as part of said detector circuit for providing hysteresis characteristics thereto so that said detector circuit can retain data read immediately before; and means for monitoring the potentials of said word lines and effecting a flow of current for providing the aforesaid hysteresis characteristics only when all the word line potentials are lower than a predetermined potential.
Claim 5
Dependent Claim
25 words
A semiconductory memory as set forth in claim 2, wherein said means for providing hysteresis characteristics include a pair of transistors having their bases cross-connected.
Claim 6
Dependent Claim
37 words
A semiconductory memory as set forth in claim 3, wherein said means for monitoring the potentials of said word lines and effecting a flow of current for providing said hysteresis characteristics includes a hysteresis characteristic control circuit.
Claim 7
Dependent Claim
37 words
A semiconductory memory as set forth in claim 2, wherein said means for monitoring the potentials of said word lines and effecting a flow of current for providing said hysteresis characteristics includes a hysteresis characteristic control circuit.
References Cited (Backward Citations)
US4297598A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-10-10 | 1987-04-11 | 1987-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-10-10 | 1991-04-11 | 1991-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-10-10 | 1995-04-11 | 1995-10-11 | $7700.00 | Window Closed / Lapsed |