Method and apparatus for inserting instructions in a control sequence in a stored program controlled telecommunications system

Claim 2

In a stored program controlled equipment having an operating device to be controlled, a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses within one of the sequences establishes the clock pulse period of the equipment, an addressed memory means having a plurality of addressed memory element groups for storing control instructions which are read in response to received addresses, an address generator means responsive to said timing pulse for sequentially emitting to the addressed memory means the addresses of the memory element groups to be read, and an instruction decoder means for generating control signals for controlling the operating device, the method of introducing one of a plurality of insertion instructions at one point in the sequence of control instructions, said method comprising the steps of storing in one of the addressed memory element groups the insertion instruction for controlling the testing of the operating device, storing in at least one of the addressed memory element groups an insertion reference instruction routine associated with the fetching of the insertion instruction and the address of the next instruction of the sequence of control instructions, upon reading the insertion reference instruction routine momentarily stopping the operation of the address generator means and during such stopping fetching the insertion instruction from the addressed memory means for transfer to the decoder means, then inserting the address of said next instruction of the sequence of control instructions into the address generator means, and then restarting the address generator means.

Claim 3

The method of claim 1 wherein said step of storing in at least one of the addressed memory element groups comprises storing in a selectable register means the address of said one of the addressed memory element groups, and storing in at least one of the memory element groups indicia for selecting the selectable register means and the address of the next instruction of the sequence of control instructions; and said step of fetching the insertion instruction comprises selecting the register means to transfer the address stored therein to said addressed memory means to read and transfer the insertion instruction for controlling the testing of the operating device to the decoder means.

Claim 4

The method of claim 1 wherein the same memory element group stores the indicia for selecting the selectable register means and the address of the next instruction of the sequence of control instructions.

Claim 5

In a stored program controlled equipment having: an operating device to be controlled; a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses establish the clock pulse period of the equipment; an addressed memory means having an address input, an instruction output and a plurality of addressed memory element group for storing control instructions which are read in response to received addresses; an address generator means being responsive to the timing pulses for sequentially generating the addresses of the memory element groups to be read, having an input means for receiving addresses, and having a first output and a second output for transmitting therefrom the address received at its input means and the address being subsequent to the address received, respectively; and an instruction decoder means having an input which is connected to the instruction output of the addressed memory means, and a plurality of outputs for generating control signals for at least controlling the operating device, apparatus for introducing one of a plurality of insertion instructions at a point in a sequence of control instructions, said apparatus comprising: a first memory element group in the addressed memory means for storing the insertion instruction; a second memory element group in the addressed memory means having an address at said point in the sequence of control instructions, said second memory element group storing first indicia for indicating that an insertion instruction is to be performed, and second indicia for indicating that the address of said first memory element group should be fetched; a third memory element group in the addressed memory means having the next address after the point, said third memory element group storing said first indicia and third indicia for indicating that the address of the next control instruction in the sequence should be fetched; an address transmitter means having first and second address output means for transmitting, in response to the second and third indicia, the address of said first memory element group and the address of said next control instruction, respectively; a logical switching means having two address inputs for receiving addresses, the first being connected to the second output of the address generator means and the second being connected to both address output means of said address transmitter means, an output for transmitting the address received by one of the address inputs, said output being connected to the input means of said address generator means, and a control input for controlling which of the received addresses is transmitted in response to said first indicia; and a buffer register means having an input for receiving information connected to the first output of the address generator means, and having an output for delayed transmitting therefrom the information received at its input, said output being connected to the address input of the addressed memory means, whereby the second memory element group, the third memory element group, the first memory element group and the next control instruction in the sequence are addressed successively.

Claim 6

In a stored program controlled equipment having: an operating device to be controlled; a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses establish the clock pulse period of the equipment; an addressed memory means having an address input, an instruction output and a plurality of addressed memory element group for storing control instructions which are read in response to received addresses; an address generator means being responsive to the timing pulses for sequentially generating the addresses of the memory element groups to be read, having an input means for receiving addresses, and having a first output and a second output for transmitting therefrom the address received at its input means and the address being subsequent to the address received, respectively; and an instruction decoder means having an input which is connected to the instruction output of the addressed memory means, and a plurality of outputs for generating control signals for at least controlling the operating device, apparatus for introducing one of a plurality of insertion instructions at a point in a sequence of control instructions, said apparatus comprising: a first memory element group in the addressed memory means for storing the insertion instruction; a second memory element group in the addressed memory means having an address at said point in the sequence of control instructions, said second memory element group storing first indicia for indicating that an insertion instruction is to be performed, and second indicia for indicating that the address of said first memory element group should be fetched; a third memory element group in the addressed memory means having the next address after the point, said third memory element group storing said first indicia and third indicia for indicating that the address of the next control instruction in the sequence should be fetched; an address transmitter means having first and second address output means for transmitting, in response to the second and third indicia, the address of said first memory element group and the address of said next control instruction, respectively; a logical switching means having two address inputs for receiving addresses, the first being connected to the second output of the address generator means and the second being connected to both address output means of said address transmitter means, an output for transmitting the address received by one of the address inputs, said output being connected to the input means of said address generator means, and a control input for controlling which of the received addresses is transmitted in response to said first indicia; and a buffer register means having an input for receiving information connected to the first output of the address generator means, and having an output for delayed transmitting therefrom the information received at its input, said output being connected to the address input of the addressed memory means, whereby the second memory element group, the third memory element group, the first memory element group and the next control instruction in the sequence are addressed successively.

Claim 7

In a stored program controlled equipment having: an operating device to be controlled; a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses establish the clock pulse period of the equipment; an addressed memory means having an address input, an instruction output and a plurality of addressed memory element groups for storing control instructions which are read in response to received addresses; an address generator means being responsive to the timing pulses for sequentially generating the addresses of the memory element groups to be read, having an input means for receiving addresses, and having a first output and a second output for transmitting therefrom the address received at its input means and the address being subsequent to the address received, respectively, said first output being connected to the address input of the addressed memory means; and an instruction decoder means having an input and a plurality of outputs for generating control signals for at least controlling the output device, apparatus for introducing one of a plurality of insertion instructions at a point in a sequence of control instructions, said apparatus comprising: a first memory element group in the addressed memory means for storing the insertion instruction; a second memory element group in the addressed memory means having an address at said point in the sequence of control instructions, said second memory element group storing first indicia for indicating that an insertion instruction is to be performed, and second indicia for indicating that the address of said first memory element group should be fetched; a third memory element group in the addressed memory means having the next address after the point, said third memory element group storing said first indicia and third indicia for indicating that the address of the next control instruction in the sequence should be fetched; an address transmitter means having first and second address output means for transmitting, responsive to the second and third indicia, the address of said first memory element group and the address of said next control instruction, respectively; a logical switching means having two address inputs for receiving addresses, the first being connected to the second output of the address generator means and the second being connected to both address output means of said address transmitter means, an output for transmitting the address received by one of the address inputs, said output being connected to the input means of the address generator means, and a control input for controlling which of the received addresses is transmitted in response to said first indicia;

Claim 8

In a stored program controlled equipment having: an operating device to be controlled; a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses establish the clock pulse period of the equipment; an addressed memory means having an address input, an instruction output and a plurality of addressed memory element groups for storing control instructions which are read in response to received addresses; an address generator means being responsive to the timing pulses for sequentially generating the addresses of the memory element groups to be read, having an input means for receiving addresses, and having a first output and a second output for transmitting therefrom the address received at its input means and the address being subsequent to the address received, respectively, said first output being connected to the address input of the addressed memory means; and an instruction decoder means having an input and a plurality of outputs for generating control signals for at least controlling the output device, apparatus for introducing one of a plurality of insertion instructions at a point in a sequence of control instructions, said apparatus comprising: a first memory element group in the addressed memory means for storing the insertion instruction; a second memory element group in the addressed memory means having an address at said point in the sequence of control instructions, said second memory element group storing first indicia for indicating that an insertion instruction is to be performed, and second indicia for indicating that the address of said first memory element group should be fetched; a third memory element group in the addressed memory means having the next address after the point, said third memory element group storing said first indicia and third indicia for indicating that the address of the next control instruction in the sequence should be fetched; an address transmitter means having first and second address output means for transmitting, responsive to the second and third indicia, the address of said first memory element group and the address of said next control instruction, respectively; a logical switching means having two address inputs for receiving addresses, the first being connected to the second output of the address generator means and the second being connected to both address output means of said address transmitter means, an output for transmitting the address received by one of the address inputs, said output being connected to the input means of the address generator means, and a control input for controlling which of the received addresses is transmitted in response to said first indicia;

Claim 9

and a buffer register means having an input for receiving information conneted to instruction output of the addressed memory means, and having an output for delayed transmitting therefrom the information received at its input, said output being connected to the input of the instruction decoder means, whereby the second memory element group, the third memory element group, the first memory element group, and the next control instruction in the sequence are addressed successively.

Claim 10

and a buffer register means having an input for receiving information conneted to instruction output of the addressed memory means, and having an output for delayed transmitting therefrom the information received at its input, said output being connected to the input of the instruction decoder means, whereby the second memory element group, the third memory element group, the first memory element group, and the next control instruction in the sequence are addressed successively.

Claim 11

In a stored program controlled equipment having: an operating device to be controlled; a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses establish the clock pulse period of the equipment; an addressed memory means having an address input, an instruction output and a plurality of addressed memory element groups for storing control instructions which are read in response to received addresses; an address generator means being responsive to said timing pulses for sequentially generating the addresses of the memory element groups to be read, and having an input means for receiving addresses, and having a first output and a second output for transmitting therefrom the address received at its input means and the address being subsequent to the address received, respectively; and an instruction decoder means having an input which is connected to the instruction output of the addressed memory means, and a plurality of outputs for generating control signals for at least controlling the operating device, apparatus for introducing one of a plurality of insertion instructions at a point in a sequence of control instructions, said apparatus comprising: a first memory element group in the addressed memory means for storing the insertion instruction; a second memory element group in the addressed memory means having an address at said point in the sequence of control instructions, said second memory element group storing first indicia for indicating that an insertion instruction is to be performed, and second indicia for indicating that the address of said first memory element group should be fetched, and a third indicia for indicating that the address (n) of the next control instruction in the sequence should be fetched; an address transmitter means having first and second address output means for transmitting, responsive to said second and third indicia, the address of said first memory element group and the address of said next control instruction, respectively; a first logical switching means having two address inputs for receiving addresses, the first being connected to the second output of the address generator means and the second being connected to the second address output means of said address transmitter means, an output for transmitting the address received by one of the address inputs, said output is connected to the input means of the address generator means, and a control input for controlling which of the received addresses is transmitted in response to said first indicia; a second logical switching means having two address inputs for receiving addresses, the first being connected to the first output of the address generator means and the second being connected to the first address output means of the address transmitter means, an output for transmitting the address received by one of the address inputs, and a control input for controlling which of the received addresses is transmitted in response to said first indicia; and a buffer register means having an input for receiving information connected to output of said second logical switching means, and having an output for delayed transmitting therefrom the information received at its input, said output being connected to the address input of the addressed memory means, whereby the second memory element group, the first memory element group, and the next control instruction in the sequence are addressed successively.

Claim 12

In a stored program controlled equipment having: an operating device to be controlled; a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses establish the clock pulse period of the equipment; an addressed memory means having an address input, an instruction output and a plurality of addressed memory element groups for storing control instructions which are read in response to received addresses; an address generator means being responsive to said timing pulses for sequentially generating the addresses of the memory element groups to be read, and having an input means for receiving addresses, and having a first output and a second output for transmitting therefrom the address received at its input means and the address being subsequent to the address received, respectively; and an instruction decoder means having an input which is connected to the instruction output of the addressed memory means, and a plurality of outputs for generating control signals for at least controlling the operating device, apparatus for introducing one of a plurality of insertion instructions at a point in a sequence of control instructions, said apparatus comprising: a first memory element group in the addressed memory means for storing the insertion instruction; a second memory element group in the addressed memory means having an address at said point in the sequence of control instructions, said second memory element group storing first indicia for indicating that an insertion instruction is to be performed, and second indicia for indicating that the address of said first memory element group should be fetched, and a third indicia for indicating that the address (n) of the next control instruction in the sequence should be fetched; an address transmitter means having first and second address output means for transmitting, responsive to said second and third indicia, the address of said first memory element group and the address of said next control instruction, respectively; a first logical switching means having two address inputs for receiving addresses, the first being connected to the second output of the address generator means and the second being connected to the second address output means of said address transmitter means, an output for transmitting the address received by one of the address inputs, said output is connected to the input means of the address generator means, and a control input for controlling which of the received addresses is transmitted in response to said first indicia; a second logical switching means having two address inputs for receiving addresses, the first being connected to the first output of the address generator means and the second being connected to the first address output means of the address transmitter means, an output for transmitting the address received by one of the address inputs, and a control input for controlling which of the received addresses is transmitted in response to said first indicia; and a buffer register means having an input for receiving information connected to output of said second logical switching means, and having an output for delayed transmitting therefrom the information received at its input, said output being connected to the address input of the addressed memory means, whereby the second memory element group, the first memory element group, and the next control instruction in the sequence are addressed successively.

Claim 13

In a stored program controlled equipment having: an operating device to be controlled; a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses establish the clock pulse period of the equipment; an addressed memory means having an address input, an instruction output and a plurality of addressed memory element groups for storing control instructions which are read in response to received addresses; an address generator means being responsive to said timing pulses for sequentially generating the addresses of the memory element groups to be read, and having an input means for receiving addresses, and having a first output and a second output for transmitting therefrom the address received at its input means and the address being subsequent to the address received, respectively, said first output being connected to the address input of the addressed memory means; and an instruction decoder means having an input which is connected to the instruction output of the addressed memory means, and a plurality of outputs for generating control signals for at least controlling the operating device, apparatus for introducing one of a plurality of insertion instructions at a point in a sequence of control instructions, said apparatus comprising: a first memory element group in the addressed memory means for storing the insertion instruction; a second memory element group having an address at said point in the sequence of control instructions, said second memory element group storing first indicia for indicating that an insertion instruction is to be performed, second indicia for indicating that the address of said first memory element group should be fetched, and a third indicia for indicating that the address of the next control instruction in the sequence should be fetched; an address transmitter means having first and second address output means for transmitting, responsive to the second and third indicia, the address of said first memory element group and the address of said next control instruction, respectively, said first address output means being connected to the input means of the address generator means; a logical switching means having two address inputs for receiving addresses, the first being connected to the second output of the address generator means, an output for transmitting the address received by one of the address inputs, said output being connected to the input means of the address generator means, and a control input for controlling which of the received addresses is transmitted in response to said first indicia; and a buffer register means having an input for receiving information connected to the second address output means of the address transmitter means, and having an output for transmitting therefrom the information received at its input, said output being connected to the second address input of the logical switching means, whereby the second memory element group, the first memory element group and the next control instruction in the sequence are addressed successively.

Claim 14

In a stored program controlled equipment having: an operating device to be controlled; a clock pulse generator for generating sequences of timing pulses wherein adjacent timing pulses establish the clock pulse period of the equipment; an addressed memory means having an address input, an instruction output and a plurality of addressed memory element groups for storing control instructions which are read in response to received addresses; an address generator means being responsive to said timing pulses for sequentially generating the addresses of the memory element groups to be read, and having an input means for receiving addresses, and having a first output and a second output for transmitting therefrom the address received at its input means and the address being subsequent to the address received, respectively, said first output being connected to the address input of the addressed memory means; and an instruction decoder means having an input which is connected to the instruction output of the addressed memory means, and a plurality of outputs for generating control signals for at least controlling the operating device, apparatus for introducing one of a plurality of insertion instructions at a point in a sequence of control instructions, said apparatus comprising: a first memory element group in the addressed memory means for storing the insertion instruction; a second memory element group having an address at said point in the sequence of control instructions, said second memory element group storing first indicia for indicating that an insertion instruction is to be performed, second indicia for indicating that the address of said first memory element group should be fetched, and a third indicia for indicating that the address of the next control instruction in the sequence should be fetched; an address transmitter means having first and second address output means for transmitting, responsive to the second and third indicia, the address of said first memory element group and the address of said next control instruction, respectively, said first address output means being connected to the input means of the address generator means; a logical switching means having two address inputs for receiving addresses, the first being connected to the second output of the address generator means, an output for transmitting the address received by one of the address inputs, said output being connected to the input means of the address generator means, and a control input for controlling which of the received addresses is transmitted in response to said first indicia; and a buffer register means having an input for receiving information connected to the second address output means of the address transmitter means, and having an output for transmitting therefrom the information received at its input, said output being connected to the second address input of the logical switching means, whereby the second memory element group, the first memory element group and the next control instruction in the sequence are addressed successively.