Video character generator

Claim 2

In display enhancement apparatus for use in a video display system having circuitry for producing digital signals having first and second values representative of a video character, said apparatus having at least one delay means for generating delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of one horizontal scan line and a clock signal generator for generating clocking signals in synchronism with said digital signals, the improvement comprising, gate means responsive to said digital signals and said delayed signals comprising said character for producing an output when said signals have said first value, a parallel-loading shift register responsive to said output for loading a predetermined pattern of digital information into each stage of said register, and responsive to said clocking signals for shifting said predetermined pattern through said register stages, and means responsive to the digital information stored in one of said shift register stages for generating a background signal output.

Claim 3

In display enhancment apparatus, the improvement according to claim 1 wherein one of said shift register stages has an output for producing a signal equivalent to the information stored in said one stage and the improvement further comprises, pattern generating means responsive to said signal and said delayed signal for producing a character body signal, and means responsive to the signal at said shift register output and said character body signal for generating a composite video signal output.

Claim 4

Display enhancement apparatus for use in a video display system having circuitry for producing digital signals representative of a video character and clock signal generation circuitry, said apparatus comprising at least two delay means for generating delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of one horizontal scan line and twice-delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of two horizontal scan lines, gate means responsive to digital character information in said signal, said delayed signal and said twice-delayed signal for producing a first output and responsive to the absence of character information in said signal, said delayed signal and said twice-delayed signal for producing a second output, a parallel-loading shift register responsive to said first output for loading a predetermined pattern of digital information into each stage of said register, and responsive to said second output and said clock signals for shifting said predetermined pattern through said register stages, one of said shift register stages having an output for producing a signal equivalent to the information stored in said one stage, pattern generating means responsive to said signals and said delayed signals for producing a character body signal, and means responsive to the signal at said shift register output and said character body signal for generating a composite video signal output.

Claim 5

Display enhancement apparatus for use in a video display system having circuitry for producing digital signals representative of a video character and clock signal generation circuitry, said apparatus comprising at least two delay means for generating delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of one horizontal scan line and twice-delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of two horizontal scan lines, gate means responsive to digital character information in said signal, said delayed signal and said twice-delayed signal for producing a first output and responsive to the absence of character information in said signal, said delayed signal and said twice-delayed signal for producing a second output, a parallel-loading shift register responsive to said first output for loading a predetermined pattern of digital information into each stage of said register, and responsive to said second output and said clock signals for shifting said predetermined pattern through said register stages, one of said shift register stages having an output for producing a signal equivalent to the information stored in said one stage, pattern generating means responsive to said signals and said delayed signals for producing a character body signal, and means responsive to the signal at said shift register output and said character body signal for generating a composite video signal output.

Claim 6

Display enhancement apparatus according to claim 3 further comprising means to vary said predetermined pattern of digital information loaded into said parallel-loading shift register in accordance with the desired character type.

Claim 7

Display enhancement apparatus according to claim 4 wherein said pattern generating means comprises, a shift register having at least a first second and third stage connected in serial order and an input, means for providing said delayed signals to the input of said shift register, and means for generating a character body signal when digital character information appears in said second shift register stage.

Claim 8

Display enhancement apparatus according to claim 5 wherein said gate means is an OR gate having a plurality of inputs and an output, each of said OR gate inputs being connected to the output of one of said delay means.

Claim 9

Display enhancement apparatus for use in a video display system having circuitry for producing digital signals having a first value representative of a video character body and a second value representative of background information and clock signal generation circuitry, said apparatus comprising a first digital delay circuit having an input for receiving said digital signals and an output for generating delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of one horizontal scan line, a second digital delay circuit having an input connected to the output of said first delay circuit and an output for generating twice-delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of two horizontal scan lines, a first NAND gate having three inputs and an output, one of said first NAND gate inputs being connected to said display system for receiving said digital signals, a second of said first NAND gate inputs being connected to the output of said first delay circuit and a third one of said first NAND gate inputs being connected to the output of said second delay circuit, a parallel-loading shift register having at least a first, a second and a third stage connected in serial order, an input, a load/shift control input and a clock input, said shift register input being connected to a digital signal source having said second value, said load/shift control input being connected to said output of said first NAND gate and said clock input being connected to said display system for receiving said clock signals, pattern generating means responsive to said signals and said delayed signals for producing a character body signal, and a second NAND gate having two inputs and an output, one of said second NAND gate inputs being connected to said shift register third stage and the other of said second NAND gate inputs being connected to said pattern generating means.

Claim 10

Display enhancement apparatus for use in a video display system having circuitry for producing digital signals having a first value representative of a video character body and a second value representative of background information and clock signal generation circuitry, said apparatus comprising a first digital delay circuit having an input for receiving said digital signals and an output for generating delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of one horizontal scan line, a second digital delay circuit having an input connected to the output of said first delay circuit and an output for generating twice-delayed signals which are equivalent to said signals delayed by a time interval equal to the time duration of two horizontal scan lines, a first NAND gate having three inputs and an output, one of said first NAND gate inputs being connected to said display system for receiving said digital signals, a second of said first NAND gate inputs being connected to the output of said first delay circuit and a third one of said first NAND gate inputs being connected to the output of said second delay circuit, a parallel-loading shift register having at least a first, a second and a third stage connected in serial order, an input, a load/shift control input and a clock input, said shift register input being connected to a digital signal source having said second value, said load/shift control input being connected to said output of said first NAND gate and said clock input being connected to said display system for receiving said clock signals, pattern generating means responsive to said signals and said delayed signals for producing a character body signal, and a second NAND gate having two inputs and an output, one of said second NAND gate inputs being connected to said shift register third stage and the other of said second NAND gate inputs being connected to said pattern generating means.

Claim 11

Display enhancement apparatus according to claim 7 further comprising means to vary said predetermined pattern of digital information loaded into said parallel-loading shift register in accordance with the desired character type.

Claim 12

Display enhancement apparatus according to claim 8 wherein said varying means comprises means for generating a digital signal having a first value for one clock period and an OR gate having two inputs and an output, one of said OR gate inputs being connected to said display system for receiving said digital signals, the other of said OR gate inputs being connected to said generating means and said OR gate output being connected to the parallel load input of said third shift register stage.

Claim 13

Display enhancement apparatus according to claim 9 wherein said pattern generating means comprises, a shift register having at least a first second and third stage connected in serial order and an input, means for providing said delayed signals to the input of said shift register, and means for generating a character body signal when digital character information appears in said second shift register stage.