Keyboard switch circuit

Claim 2

A keyboard switch circuit comprising: a switch matrix circuit having 2 m columns and (2 n-1 +2) to 2 n rows, where m and n represent positive integers greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows: circuit means for sequentially applying pulses to the respective rows; a first set of m logic gates each connected to selected ones of 2 m-1 columns; a logic circuit having 2 m inputs each connected to a different one of said columns; a second set of n logic gates each connected to a selected one or ones of the rows; a third set of n logic gates each having first and second inputs, said first inputs of said third set of logic gates each being connected to the output of a different one of the second set of logic gates, and said second inputs being connected to the output of said logic circuit having 2 m inputs, whereby each logic gate of said third set of logic gates in ON only when the logic state of the gate of the second set of logic gates connected to the logic gate and the logic state of the logic circuit having 2 m inputs are coincident with each other; and (m+n) outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which m outputs are the respective outputs of the first set of logic gates and n outputs are the respective outputs of the third set of logic gates.

Claim 3

A keyboard switch circuit according to claim 1 wherein said logic circuit having 2 m inputs and each gate in said second set of logic gates include non-inverted OR gates, and each gate in said third set of logic gates includes a non-inverted AND gate.

Claim 4

A keyboard switch circuit according to claim 2 wherein each gate in said first set of logic gates includes an OR gate.

Claim 5

A keyboard switch circuit according to claim 1 wherein each gate in said first set of logic gates includes an inverted OR gate, and wherein the circuit further comprises a set of m inverters connected to respective ones of said inverted OR gates.

Claim 6

A keyboard switch circuit according to claim 1 wherein said logic circuit having 2 m inputs, each gate in said second set of logic gates and each gate in said third set of logic gates include inverted OR gates.

Claim 7

A keyboard switch circuit according to claim 5 wherein each gate in said first set of logic gates includes a non-inverted OR gate.

Claim 8

A keyboard switch circuit according to claim 5 wherein each gate in said first set of logic gates is an inverted OR gate; and wherein the switch circuit further comprises a set of m inverters each connected to an output of a different one of said inverterd OR gates in said first set.

Claim 9

A keyboard switch circuit comprising: a switch matrix circuit having 2 m columns and (2 n +1) rows, where m and n represent positive integers greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a further set of m logic gates each connected to selected ones of 2 m-1 columns; a logic circuit having 2 m inputs each connected to a different one of said columns; a second set of n logic gates each connected to a selected one or ones the rows; a third set of (n+1) logic gates each having first and second inputs, said first inputs of n of said third set of logic gates each being connected to a different one of the second set of logic gates, said first input of said remaining one logic gate being directly connected to one of said rows and said second input of all said logic gates of said third set being connected to the output of the logic circuit having 2 m inputs whereby each logic gate of said third set of logic gates is ON only when the logic state of the gate of the second set of logic gates connected to the logic gate of said third set of logic gates and the logic state of the logic circuit having 2 m inputs are coincident with each other; and (m+n+1) outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which m outputs are the respective outputs of the first set of logic gates and (n+1) outputs are the respective outputs of the third set of logic gates.

Claim 10

A keyboard switch circuit comprising: a switch matrix circuit having 2 m columns and (2 n +1) rows, where m and n represent positive integers greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a further set of m logic gates each connected to selected ones of 2 m-1 columns; a logic circuit having 2 m inputs each connected to a different one of said columns; a second set of n logic gates each connected to a selected one or ones the rows; a third set of (n+1) logic gates each having first and second inputs, said first inputs of n of said third set of logic gates each being connected to a different one of the second set of logic gates, said first input of said remaining one logic gate being directly connected to one of said rows and said second input of all said logic gates of said third set being connected to the output of the logic circuit having 2 m inputs whereby each logic gate of said third set of logic gates is ON only when the logic state of the gate of the second set of logic gates connected to the logic gate of said third set of logic gates and the logic state of the logic circuit having 2 m inputs are coincident with each other; and (m+n+1) outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which m outputs are the respective outputs of the first set of logic gates and (n+1) outputs are the respective outputs of the third set of logic gates.

Claim 11

A keyboard switch circuit according to claim 8 wherein said logic circuit having 2 m inputs and each gate in said second set of gates include non-inverted OR gates, and each gate in said third set of logic gates includes a non-inverted AND gate.

Claim 12

A keyboard switch circuit accordng to claim 9 wherein each gate in said first set of logic gates includes a non-inverted OR gate.

Claim 13

A keyboard switch circuit according to claim 9 wherein each gate in said first set of logic gates includes an inverted OR gate, and wherein the circuit further comprises a set of m inverters each connected to an output of a different one of said inverted OR gates.

Claim 14

A keyboard switch circuit according to claim 8 wherein said logic circuit having 2 m inputs, each gate in said second set of logic gates and each gate in said third set of logic gates include inverted OR gates, and wherein the circuit further comprises an inverter between said remaining one logic gate and the row connected to the gate.

Claim 15

A keyboard switch circuit according to claim 12 wherein each gate in said first set of logic gates includes a non-inverted OR gate.

Claim 16

A keyboard switch circuit according to claim 12 wherein each gate in said first set of logic gates includes an inverted OR gate, and wherein the circuit further comprises a set of m inverters each connected to an output of a different one of said inverted OR gates in said first set.

Claim 17

A keyboard switch circuit comprising: a switch matrix circuit having 2 columns and (2 -1 +2 n ) to 2 n rows, where n represents a positive integer greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a logic circuit having 2 inputs each connected to a different one of said columns; a conductor connected to one of said columns; a first set of n logic gates each connected to a selected one or ones of the rows; a second set of n logic gates each having first and second inputs, said first inputs of said second set of logic gates each being connected to the output of a different one of the first set of n logic gates and said second input of each of said second set of logic gates being connected to the output of said logic circuit having 2 inputs, whereby each logic gate is ON only when the logic state of the gate of the first set of logic gates connected to the logic gate and the logic state of the logic circuit having 2 inputs are coincident with each other; and (n+1) outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which n outputs are the respective outputs of the second set of logic gates and the remaining one output is said conductor directly connected to one of the columns.

Claim 18

A keyboard switch circuit comprising: a switch matrix circuit having 2 columns and (2 -1 +2 n ) to 2 n rows, where n represents a positive integer greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a logic circuit having 2 inputs each connected to a different one of said columns; a conductor connected to one of said columns; a first set of n logic gates each connected to a selected one or ones of the rows; a second set of n logic gates each having first and second inputs, said first inputs of said second set of logic gates each being connected to the output of a different one of the first set of n logic gates and said second input of each of said second set of logic gates being connected to the output of said logic circuit having 2 inputs, whereby each logic gate is ON only when the logic state of the gate of the first set of logic gates connected to the logic gate and the logic state of the logic circuit having 2 inputs are coincident with each other; and (n+1) outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which n outputs are the respective outputs of the second set of logic gates and the remaining one output is said conductor directly connected to one of the columns.

Claim 19

A keyboard switch circuit according to claim 15 wherein said logic circuit having 2 inputs and each gate in said first set of logic gates include non-inverted OR gates, and each gate in said second set of logic gates includes a non-inverted AND gate.

Claim 20

A keyboard switch circuit according to claim 15 wherein said logic circuit having 2 inputs, each gate in said first set of logic gates and each gate in said second set of logic gates include inverted OR gates.

Claim 21

A keyboard switch circuit comprising: a switch matrix circuit having 2 columns and (2 n +1) rows, wherein n represents positive integers greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a logic circuit having 2 inputs each connected to a different one of said columns; a conductor connected to one of said columns; a first set of n logic gates each connected to a selected one or ones of the rows; a second set of (n+1) logic gates each having first and second inputs, said first inputs of n of said second set of logic gates each being connected to a different one of the first set of logic gates, said first input of said remaining one logic gate being directly connected to one of said rows and second input of all said logic gates of said second set being connected to the output of the logic circuit having 2 inputs whereby each logic gate is ON only when the logic state of the gate of the first set of logic gates associated with the logic gate and the logic state of the logic circuit having 2 inputs are coincident with each other; and (n+2) outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which one output is said conductor connected to one of the columns and the remaining outputs are the respective outputs of the second set of logic gates.

Claim 22

A keyboard switch circuit comprising: a switch matrix circuit having 2 columns and (2 n +1) rows, wherein n represents positive integers greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a logic circuit having 2 inputs each connected to a different one of said columns; a conductor connected to one of said columns; a first set of n logic gates each connected to a selected one or ones of the rows; a second set of (n+1) logic gates each having first and second inputs, said first inputs of n of said second set of logic gates each being connected to a different one of the first set of logic gates, said first input of said remaining one logic gate being directly connected to one of said rows and second input of all said logic gates of said second set being connected to the output of the logic circuit having 2 inputs whereby each logic gate is ON only when the logic state of the gate of the first set of logic gates associated with the logic gate and the logic state of the logic circuit having 2 inputs are coincident with each other; and (n+2) outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which one output is said conductor connected to one of the columns and the remaining outputs are the respective outputs of the second set of logic gates.

Claim 23

A keyboard switch circuit according to claim 18 wherein said logic circuit having 2 inputs and each gate in said first set of logic gates include non-inverted AND gates.

Claim 24

A keyboard switch circuit according to claim 18 wherein said logic circuit having 2 inputs, each gate in said first set of logic gates and each gate in said second set of logic gates include inverted OR gates.

Claim 25

A keyboard switch circuit comprising: a switch matrix circuit having 2 m columns and 2 to 3 rows, where m represents positive integers greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a first set of m logic gates each connected to selected ones of 2 m-1 columns; a logic circuit having 2 m inputs each connected to a different one of said columns; a second set of k logic gates where k equals the number of rows minus one, each of said second set of logic gates having first and second inputs, said first inputs of said gates each being connected to a selected one or ones of the rows and said second inputs each being connected to the output of said logic circuit having 2 m inputs whereby each logic gate is ON only when the logic state of its first input and the logic state of the logic circuit having 2 m inputs are coincident with each other; and m+k outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which m outputs are the respective outputs of the first set of logic gates and the k remaining outputs are the respective outputs of said second set of logic gates.

Claim 26

A keyboard switch circuit comprising: a switch matrix circuit having 2 m columns and 2 to 3 rows, where m represents positive integers greater than or equal to 2, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a first set of m logic gates each connected to selected ones of 2 m-1 columns; a logic circuit having 2 m inputs each connected to a different one of said columns; a second set of k logic gates where k equals the number of rows minus one, each of said second set of logic gates having first and second inputs, said first inputs of said gates each being connected to a selected one or ones of the rows and said second inputs each being connected to the output of said logic circuit having 2 m inputs whereby each logic gate is ON only when the logic state of its first input and the logic state of the logic circuit having 2 m inputs are coincident with each other; and m+k outputs each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which m outputs are the respective outputs of the first set of logic gates and the k remaining outputs are the respective outputs of said second set of logic gates.

Claim 27

A keyboard switch circuit according to claim 21 wherein said logic circuit having 2 m inputs include a non-inverted OR gate and each gate in said second set of logic gates includes a non-inverted AND gate.

Claim 28

A keyboard switch circuit according to claim 22 wherein said first set of logic gates includes non-inverted OR gates.

Claim 29

A keyboard switch circuit according to claim 22 wherein each gate in said first set of logic gates includes an inverted OR gate, and wherein the circuit further comprises a set of m inverters each connected to one of said inverted OR gates in said first set of logic gates.

Claim 30

A keyboard switch circuit according to claim 21 wherein said logic circuit having 2 m inputs and each gate in said second set of logic gates include inverted OR gates, wherein the circuit further comprises inverters each connected between respective first inputs of a different one of said inverted OR gates in said second set of logic gates and said rows connected to each of said first inputs of the inverted OR gates of said second set of logic gates.

Claim 31

A keyboard switch circuit according to claim 25 wherein each gate in said first set of OR gates includes a non-inverted OR gate.

Claim 32

A keyboard switch circuit according to claim 25 wherein each gate in said first set of OR gates includes an inverted OR gate, and wherein the circuit further comprises a set of m inverters each connected to an output of a different one of said inverted OR gates in said first set.

Claim 33

A keyboard switch circuit comprising: a switch matrix circuit having 2 columns and 2 to 3 rows, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a logic circuit having 2 inputs each connected to a different one of said columns; a conductor connected to one of said columns; a set of k logic gates, where k equals the number of rows minus one, each of said k logic gates having first and second inputs, said first inputs each being connected to a selected one or ones of the rows and each of said second inputs being connected to the output of said logic circuit having 2 inputs whereby each logic gate is ON only when the logic state of its first input and the logic state of the logic circuit having 2 inputs are coincident with each other; and k+1 outputs, each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which one of the outputs is said conductor directly connected to one of the columns and the remaining k outputs are the respective outputs of the set of k logic gates.

Claim 34

A keyboard switch circuit comprising: a switch matrix circuit having 2 columns and 2 to 3 rows, and a plurality of key switches, each key switch being connected across a particular one of said columns and a particular one of said rows; circuit means for sequentially applying pulses to the respective rows; a logic circuit having 2 inputs each connected to a different one of said columns; a conductor connected to one of said columns; a set of k logic gates, where k equals the number of rows minus one, each of said k logic gates having first and second inputs, said first inputs each being connected to a selected one or ones of the rows and each of said second inputs being connected to the output of said logic circuit having 2 inputs whereby each logic gate is ON only when the logic state of its first input and the logic state of the logic circuit having 2 inputs are coincident with each other; and k+1 outputs, each producing a different digit of a binary coded signal associated with the operation of a specific key switch, in which one of the outputs is said conductor directly connected to one of the columns and the remaining k outputs are the respective outputs of the set of k logic gates.

Claim 35

A keyboard switch circuit according to claim 28 wherein said logic circuit having 2 inputs includes a non-inverted OR gate and each gate in said set of k logic gates includes a non-inverted AND gate.

Claim 36

A keyboard switch circuit according to claim 28 wherein said logic circuit having 2 inputs and each gate in said set of k logic gates include inverted OR gates, and wherein the circuit further comprises inverters each connected between a different one of said respective first inputs of said inverted OR gates and said rows connected to said first inputs of said inverted OR gates.

Claim 37

A keyboard switch circuit according to any one of claims 1 to 14 and 21 to 27 wherein the jth gate in said first set of m logic gates is connected to every 2 j-1 columns at invervals of 2 j-1 columns, where j represents positive integer from one to m.

Claim 38

A keyboard switch circuit according to any one of claims 1 to 20 wherein the kth gate in said second set of n logic gates is connected to every 2 k-1 rows at intervals of 2 k-1 rows, where k represents positive integer from one to n.

Claim 39

A keyboard switch circuit according to any one of claims 1 to 14 wherein the jth gate in said first set of m logic gates is connected to every 2 j-1 columns at intervals of 2 j-1 columns, wherein j represents a positive integer from one to m, and wherein the kth gate in said set of n gates is connected to every 2 k-1 rows at intervals of 2 k-1 rows, where k represents a positive integer from one to n.

Claim 40

A keyboard switch circuit comprising: (a) a switch matrix circuit including 2 m columns, where m represents a positive integer, and (2 n-1 +1) to (2 n +1) rows, where n is a positive integer; (b) key switches each connected across a different one of said columns and a different one of said rows; (c) a circuit for sequentially applying pulses to said rows; (d) a first set of m logic gates connected to said columns, said logic gate, if m=1, being replaced by a conductor connected to selected ones of said columns; (e) a second set of n logic gates connected to a selected one or ones of said rows, if n>1 and if n=1, said second set of logic gates being empty; (f) a third set of logic gates having first and second inputs, said first inputs being connected to the outputs of said second set of n logic gates or to a selected one or ones of said rows; (g) a logic means circuit having inputs connected to each of said columns and having an output connected to each of said second inputs of said third set of logic gates; and (h) output terminals connected to each output of said third set of logic gates and to each output of said first set of logic gates if m>1 or to one of said columns if m=1.

Claim 41

A keyboard switch circuit comprising: (a) a switch matrix circuit including 2 m columns, where m represents a positive integer, and (2 n-1 +1) to (2 n +1) rows, where n is a positive integer; (b) key switches each connected across a different one of said columns and a different one of said rows; (c) a circuit for sequentially applying pulses to said rows; (d) a first set of m logic gates connected to said columns, said logic gate, if m=1, being replaced by a conductor connected to selected ones of said columns; (e) a second set of n logic gates connected to a selected one or ones of said rows, if n>1 and if n=1, said second set of logic gates being empty; (f) a third set of logic gates having first and second inputs, said first inputs being connected to the outputs of said second set of n logic gates or to a selected one or ones of said rows; (g) a logic means circuit having inputs connected to each of said columns and having an output connected to each of said second inputs of said third set of logic gates; and (h) output terminals connected to each output of said third set of logic gates and to each output of said first set of logic gates if m>1 or to one of said columns if m=1.