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US4408131A Expired / Lapsed US ⏱️ 0.0 years remaining

Optically isolated solid state relay

Assignee: Sundstrand Corp
•
Filing: 1981-09-21
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Granted: 1983-10-04
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Expires: 2001-09-21
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Abstract

Abstract A solid state relay is provided with a control logic circuit which receives a low level input control signal and controls a power field effect transistor (FET) switching element by means of an optical isolator. Connecting an external power source to a function selecting input terminal causes the relay to operate as a normally open, normally closed, or latching relay. A voltage spike suppression network protects the FET from voltage spikes appearing across it.

Inventors

  • 👤 David A. Fox

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 16:00
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/78; H03K17/785

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 263 words
A solid state relay comprising: sensing means for responding to an input voltage signal by producing a logic signal of a relatively fixed magnitude; a logic gate having a first input terminal operatively connected to receive said logic signal from said sensing means, an output terminal, and a second input terminal; said second input terminal having a fixed interconnection to means for generating a first signal changing in logic state only upon a predetermined change in the waveform of said logic signal from said sensing means; means for selectively overriding said first signal connected to said second input terminal; a light emitting diode responsive to said logic first signal appearing at said output terminal for generating radiation; an array of photodiodes connected in series between a pair of array electrodes and operatively coupled to said light emitting diode for developing a control voltage across said array electrodes in response to radiation from said light emitting diode; a field effect transistor including a pair of current carrying electrodes, a gate electrode and a substrate electrode, one of said array electrodes connected to said gate electrode and the other of said array electrodes connected to said substrate electrode whereby the impedance between said current carrying electrodes has one value in the absence of and a greatly different value in the presence of said control voltage between said gate electrode and said substrate electrode; means for providing a large resistive impedance between said gate electrode and said substrate electrode; and a pair of output terminals, each connected to a respective one of said current carrying electrodes.
Claim 2
Dependent Claim 263 words
A solid state relay comprising: sensing means for responding to an input voltage signal by producing a logic signal of a relatively fixed magnitude; a logic gate having a first input terminal operatively connected to receive said logic signal from said sensing means, an output terminal, and a second input terminal; said second input terminal having a fixed interconnection to means for generating a first signal changing in logic state only upon a predetermined change in the waveform of said logic signal from said sensing means; means for selectively overriding said first signal connected to said second input terminal; a light emitting diode responsive to said logic first signal appearing at said output terminal for generating radiation; an array of photodiodes connected in series between a pair of array electrodes and operatively coupled to said light emitting diode for developing a control voltage across said array electrodes in response to radiation from said light emitting diode; a field effect transistor including a pair of current carrying electrodes, a gate electrode and a substrate electrode, one of said array electrodes connected to said gate electrode and the other of said array electrodes connected to said substrate electrode whereby the impedance between said current carrying electrodes has one value in the absence of and a greatly different value in the presence of said control voltage between said gate electrode and said substrate electrode; means for providing a large resistive impedance between said gate electrode and said substrate electrode; and a pair of output terminals, each connected to a respective one of said current carrying electrodes.
Claim 3
Dependent Claim 28 words
A solid state relay as recited in claim 1, wherein said means for generating said first signal comprises a flip-flop circuit operatively connected to receive said logic signal.
Claim 4
Dependent Claim 26 words
A solid state relay as recited in claim 2, wherein said means for selectively overriding said first signal includes a reset input on said flip-flop circuit.
Claim 5
Dependent Claim 31 words
A solid state relay as recited in claim 1 wherein the connection of a direct voltage to said means for selectively overriding said first signal provides unlatched operation of said relay.
Claim 6
Dependent Claim 26 words
A solid state relay as recited in claim 1, further comprising means for filtering said logic signal, connected between said sensing means and said logic gate.
Claim 7
Dependent Claim 79 words
A solid state relay as recited in claim 5, wherein said means for filtering comprises: a second logic gate having an input connection and an output connection; two resistors connected in series with said input connection; a capacitor connected to the common point between said two resistors; said logic signal being connected to said series connection of said two resistors; and having a third resistor connected between said input connection and said output connection of said second logic gate.
Claim 8
Dependent Claim 21 words
A solid state relay as recited in claim 1 further comprising means for suppressing voltage spikes on said current carrying electrodes.
Claim 9
Dependent Claim 71 words
A solid state relay as recited in claim 7 wherein said means for suppressing voltage spikes comprises: a circuit branch connected between said gate electrode and one of said current carrying electrodes; said circuit branch including the series connection of a diode and a zener diode; and a resistor having one end connected to the common point between said diodes and a second end connected to the other current carrying electrode.

References Cited (Backward Citations)

US3963947A Cited
US4188547A Cited
US4227098A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1986-10-03 1987-04-04 1987-10-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1990-10-03 1991-04-04 1991-10-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1994-10-03 1995-04-04 1995-10-04 $7700.00 Window Closed / Lapsed

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