US4407005A
Expired / Lapsed
US
⏱️ 0.0 years remaining
N-Channel JFET device having a buried channel region, and method for making same
Assignee: Texas Instruments Inc
•
Filing: 1981-10-05
•
Granted: 1983-09-27
•
Expires: 2001-10-05
Abstract
Abstract A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface of the body outside the p-well. A buried channel connects the source and drain. A p-layer above the buried channel forms the top gate. Gate leakage current and noise are very low.
Inventors
- 👤 Kenneth M. Bell
- 👤 Joe R. Trogolo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:39
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D30/00; H10D30/80; H10D30/83; H10D62/00; H10D62/10; H10D62/17; H10D62/343
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
136 words
An N-channel junction field effect transistor comprising: (a) a P-type semiconductor substrate; (b) an N-type epitaxial layer on one surface of said substrate; (c) a first P-type gate region formed as a well in said N-type epitaxial region, said first P-type region comprising the bottom gate for said transistor; (d) a second P-type gate region formed at the surface of said substrate; (e) an N-type channel region buried beneath said second P-type gate region and above said first P-type region, said N-type channel region extending partially outside said first P-type region; and (f) an N-type source region at the surface of said epitaxial layer and surrounded by said P-type regions, said N-type channel region providing electrical communication between said N-type source region and said N-type epitaxial layer, said N-type epitaxial layer operative as a drain region.
Claim 2
Dependent Claim
136 words
An N-channel junction field effect transistor comprising: (a) a P-type semiconductor substrate; (b) an N-type epitaxial layer on one surface of said substrate; (c) a first P-type gate region formed as a well in said N-type epitaxial region, said first P-type region comprising the bottom gate for said transistor; (d) a second P-type gate region formed at the surface of said substrate; (e) an N-type channel region buried beneath said second P-type gate region and above said first P-type region, said N-type channel region extending partially outside said first P-type region; and (f) an N-type source region at the surface of said epitaxial layer and surrounded by said P-type regions, said N-type channel region providing electrical communication between said N-type source region and said N-type epitaxial layer, said N-type epitaxial layer operative as a drain region.
Claim 3
Dependent Claim
19 words
A transistor as in claim 1, wherein said transistor is integrated on a monolithic semiconductor substrate with bipolar circuitry.
References Cited (Backward Citations)
US4314267A
Cited
US4322738A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-26 | 1987-03-28 | 1987-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-26 | 1991-03-28 | 1991-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-26 | 1995-03-28 | 1995-09-27 | $7700.00 | Window Closed / Lapsed |