US4405983A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Auxiliary memory for microprocessor stack overflow
Assignee: AT&T Inc
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Filing: 1980-12-17
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Granted: 1983-09-20
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Expires: 2000-12-17
Abstract
Abstract A microprocessor system that provides protection against memory violations by interrupting the central processing unit (CPU). A problem arises when the interrupt itself causes memory violations in push-down stack operations. This problem is solved by providing an auxiliary memory to store stack overflow data. Memory violations are detected (30, 40) and overflow data is written (42, 60, 33, 100) into auxiliary memory, at sequential locations (50, 51, 60). An interrupt signal is returned (30, 20) to the CPU. A stack overflow interrupt program reads the number of locations written (50, 80, 90), and accesses the auxiliary memory (100, 60, 70, 90) to determine and correct the cause of the overflow.
Inventors
- 👤 Pedro I. Perez-Mendez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:32
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F7/785; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4486
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
105 words
A computer system comprising a central processing unit (CPU), a main memory having protected areas of storage and unprotected areas of storage and a memory block of defined size in an unprotected area for storing CPU interrupt data, an auxiliary memory, means for detecting an attempt by the CPU to write data into a protected area of the main memory and for interrupting the CPU in response thereto, means for detecting an overflow of the memory block occurring during the storing of interrupt data in the memory block, and means responsive to the last-mentioned detecting means for writing the overflow data into the auxiliary memory.
Claim 2
Dependent Claim
105 words
A computer system comprising a central processing unit (CPU), a main memory having protected areas of storage and unprotected areas of storage and a memory block of defined size in an unprotected area for storing CPU interrupt data, an auxiliary memory, means for detecting an attempt by the CPU to write data into a protected area of the main memory and for interrupting the CPU in response thereto, means for detecting an overflow of the memory block occurring during the storing of interrupt data in the memory block, and means responsive to the last-mentioned detecting means for writing the overflow data into the auxiliary memory.
Claim 3
Dependent Claim
34 words
A computer system as set forth in claim 1 wherein said means for writing further includes means for writing a plurality of said data into a corresponding plurality of locations in the auxiliary memory.
Claim 4
Dependent Claim
32 words
A computer system as set forth in claim 2 further comprising means responsive to said means for writing said plurality of data for communicating to the CPU the quantity of data written.
Claim 5
Dependent Claim
23 words
A computer system as set forth in claim 1 further comprising means for providing read/write access to the auxiliary memory by the CPU.
Claim 6
Dependent Claim
42 words
A computer system as set forth in claim 4 further comprising means responsive to control data from the CPU for enabling said means for writing data into the auxiliary memory and for enabling, in the alternative, said means for providing read/write access.
Claim 7
Dependent Claim
86 words
A computer system as set forth in claim 1 wherein said means for writing further includes means for writing a plurality of said data in a corresponding plurality of locations in the auxiliary memory, and said computer system further comprises means for providing read/write access to the auxiliary memory by the CPU, and means for enabling said means for writing data into the auxiliary memory and said means for writing a plurality of data, and for enabling, in the alternative, said means for providing read/write access.
Claim 8
Dependent Claim
66 words
A computer system comprising a central processing unit (CPU) controllable by interrupts, a main memory having a storage block for storing interrupt data from the CPU during an interrupt, an auxiliary memory, means for detecting an overflow state of the storage block during the storing of CPU interrupt data therein, and means responsive to the detecting means for diverting the overflow data to the auxiliary memory.
Claim 9
Dependent Claim
66 words
A computer system comprising a central processing unit (CPU) controllable by interrupts, a main memory having a storage block for storing interrupt data from the CPU during an interrupt, an auxiliary memory, means for detecting an overflow state of the storage block during the storing of CPU interrupt data therein, and means responsive to the detecting means for diverting the overflow data to the auxiliary memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-19 | 1987-03-21 | 1987-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-19 | 1991-03-21 | 1991-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-19 | 1995-03-21 | 1995-09-20 | $7700.00 | Window Closed / Lapsed |