Subscriber terminal for use in a time shared bidirectional digital communication network

Claim 2

A subscriber terminal for use in a bidirectional communication network in which said subscriber terminal is connected to a master terminal through a communication channel and in which said subscriber terminal receives a receive signal composed of a plurality of digital receive signal bursts from said master terminal through said channel and sends a digital send signal burst to said master terminal through said channel on a time shared basis in each frame period to carry out communication with said master terminal in a communication interval following a call originating interval, said subscriber terminal comprising first means capable of being put once in each frame period in a first mode of producing digital receive signals with a first frame phase in response to the receive signal bursts received through said channel, second means capable of being put once in each frame period in a second mode of supplying digital send signals with a second frame phase to said channel as the send signal bursts, third means responsive to said receive signals for putting said first and said second means in said first mode and out of said second mode, respectively, and then out of said first mode and in said second mode, respectively, in each frame period to synchronize said second frame phase with said first frame phase, means responsive to said receive and said send signals for carrying out said communication, and means for producing a call originating signal in said call originating interval, wherein the improvement comprises means responsive to said call originating signal for activating said third means to cause said third means to put said first and said second means temporarily out of said first mode and in said second mode, respectively, and then in said first mode and out of said second mode respectively, repeatedly until said call originating interval is followed by said communication interval, said second means supplying said call originating signal to said channel while being temporarily put in said second mode, said first means producing, while being continuously put in said first mode after being temporarily put out of said first mode, a digital receive signal with said first frame phase in response to each digital receive signal burst supplied to said channel by said master terminal in response to the call originating signal arriving thereat through said channel.

Claim 3

A subscriber terminal as claimed in claim 1, the improvement further comprising each receive signal burst having a predetermined burst length shorter than a half of said frame period and comprising a burst synchronizing bit and a predetermined number of information bits, each receive signal comprising the synchronizing and the information bits at a predetermined bit rate and with a receive bit phase dependent on a predetermined bit phase, and wherein said third means comprises: clock producing means for producing local clocks at said predetermined bit rate and with said receive bit phase; means for extracting the synchronizing bits from the respective receive signals to produce a sequence of extracted synchronizing bits with said first frame phase; resettable counting means repeatedly reset by said extracted synchronizing bits to a predetermined count representative of a local frame phase for counting said clocks from said predetermined count to successive counts representative of successive phases relative to said local frame phase to produce a first, a second, and a third timing signal representative of a first, a second, and a third preselected phase relative to said local frame phase, respectively, each of said first and said second timing signals having a duration substantially equal to said burst length; synchronism monitoring means responsive to said third timing signal and each receive signal for monitoring the synchronism of said local frame phase with said first frame phase for producing in response thereto an out of synchronism signal only when said local frame phase is out of synchronism with said first frame phase; fourth means connected to said resettable counting means and said synchronism monitoring means for putting said first means in said first mode only during presence of said first timing signal while said out of synchronism signal is absent and irrespective of states of said first through said third timing signals while said out of synchronism signal is present; and fifth means connected to said resettable counting means and said synchronism monitoring means for putting said second means in said second mode only during presence of said second timing signal while said out of synchronism signal is absent and out of said second mode irrespective of states of said first through said third timing signals while said out of synchronism signal is present.

Claim 4

A subscriber terminal as claimed in claim 2, wherein said synchronism monitoring means comprises a flip-flop responsive to said third timing signal and each receive signal for latching the synchronizing bit of said each receive signal only when said third preselected phase is in synchronism with said first frame phase for producing in response thereto said out of synchronism signal only when the last-mentioned synchronizing bit is not latched.

Claim 5

A subscriber terminal as claimed in claim 3, wherein: said resettable counting means produces a first and a second counting means output signal, said first counting means output signal being a logic "0" for representing an active state of said first timing signal, said second counting means output signal being a logic "1" for representing an active state of said second timing signal; said synchronism monitoring means producing a monitoring means output signal being a logic "0" for representing an active state of said out of synchronism signal; said fourth means comprising: a two-input AND gate supplied with said first counting means output signal and said monitoring means output signal for producing in response thereto a first output signal; and means for supplying said first output signal to said first means, said first means being put in and out of said first mode when said first output signal is at logic "0" and logic "1" levels, respectively; said fifth means comprising: a two-input AND gate supplied with said second counting means output signal and said monitoring means output signal for producing in response thereto a second output signal; and means for supplying said second output signal to said second means, said second means being put in and out of said second mode when said second output signal is at logic "1" and the logic "0" levels, respectively.

Claim 6

A subscriber terminal as claimed in claim 2, wherein said synchronism monitoring means comprises: means responsive to said third timing signal and each receive signal for producing a trigger signal only when said third preselected phase is out of synchronism with said first frame phase; and a monostable multivibrator responsive to said trigger signal for producing said out of synchronism signal during an interval of time equal to a product of said frame period and a predetermined natural number after said trigger signal is produced.

Claim 7

A subscriber terminal as claimed in claim 5, wherein: said resettable counting means produces a first and a second counting means output signal, said first counting means output signal being a logic "0" for representing an active state of said first timing signal, said second counting means output signal being a logic "1" for representing an active state of said second timing signal; said monostable multivibrator producing a monostable multivibrator output signal being a logic "0" for representing an active state of said out of synchronism signal; said fourth means comprising: a two-input AND gate supplied with said first counting means output signal and said monostable multivibrator output signal for producing in response thereto a first output signal; and means for supplying said first output signal to said first means, said first means being put in and out of said first mode when said first output signal is at logic "0" and logic "1" levels, respectively; said fifth means comprising: a two-input AND gate supplied with said second counting means output signal and said monostable multivibrator output signal for producing in response thereto a second output signal; and means for supplying said second output signal to said second means, said second means being put in and out of said second mode when said second output signal is at logic "1" and logic "0" levels, respectively.

Claim 8

A subscriber terminal as claimed in claim 2, wherein, for a case in which the synchronizing bit of each receive signal is at a logic "1" level: said resettable counting means produces a first, a second, and a third counting means output signal, said first counting means output signal being a logic "0" for representing an active state of said first timing signal, said second counting means output signal being a logic "1" for representing an active state of said second timing signal, said third timing means output signal being a logic "1" for representing an active state of said third timing signal; said synchronism monitoring means comprising: a first flip-flop having a data, a clock, and a preset input terminal for latching the synchronizing bit of each receive signal supplied to said data input terminal by the third counting means output signal supplied to said clock input terminal for thereby producing a first flip-flop output signal at logic "1" and logic "0" levels when said third preselected phase is in and out of synchronism with said first frame phase, respectively, said first flip-flop being preset by a preset input signal supplied to said preset input terminal during out of synchronism of said third preselected phase with said first frame phase thereby setting said first flip-flop output signal to a logic "1" level; a second flip-flop having a data, a clock, and a clear input terminal, said second flip-flop being cleared for producing a second flip-flop output signal at a logic "0" level when the first flip-flop output signal supplied to said clear input terminal is at a logic "0" level, said second flip-flop latching a logic "1" signal continuously supplied to said data input terminal for changing said second flip-flop output signal to a logic "1" level when the third counting means output signal supplied to said clock input terminal changes from a logic "1" level to a logic "0" level; and means for supplying the second flip-flop output signal at a logic "0" level to said preset input terminal as said preset input signal; said fourth means comprising: a single flip-flop having a data, a clock, and a clear input terminal, said single flip-flop being cleared to produce a single flip-flop output signal at a logic "0" level when the second flip-flop output signal supplied to said clear input terminal changes from a logic "1" level to a logic "0" level, said single flip-flop latching a logic "1" signal continuously supplied to said data input terminal for changing said single flip-flop output signal from a logic "0" level to a logic "1" level when the first counting means output signal supplied to said clock input terminal changes from a logic "0" level to a logic "1" level; a two-input AND gate supplied with said first counting means output signal and said single flip-flop output signal for producing in response thereto a first output signal; and means for supplying said first output signal to said first means, said first means being put in and out of said first mode when said first output signal is at logic "0" and logic "1" levels, respectively; said fifth means comprising: a two-input AND gate supplied with said second counting means output signal and said second flip-flop output signal for producing in response thereto a second output signal; and means for supplying said second output signal to said second means, said second means being put in and out of said second mode when said second output signal is at logic "1" and logic "0" levels, respectively.

Claim 9

A subscriber terminal as claimed in claim 1, the improvement further comprising each signal burst having a predetermined burst length shorter than a half of said frame period and comprising a burst synchronizing bit and a predetermined number of information bits, each receive signal comprising the synchronizing and the information bits at a predetermined bit rate and with a receive bit phase dependent on a predetermined bit phase, and wherein said third means comprises: clock producing means for producing local clocks at said predetermined bit rate and with said receive bit phase; means responsive to said clocks and each receive signal for producing an extracted synchronizing bit and a delayed synchronizing bit concurrently with appearance of the synchronizing bit in said each receive signal and one clock thereafter, respectively; resettable counting means repeatedly reset by the extracted synchronizing bits to a predetermined count representative of a local frame phase for counting said clocks from said predetermined count to successive counts representative of successive phases relative to said local frame phase to produce a first, a second, and a third timing signal representative of a first, a second, and a third preselected phase relative to said local frame phase, respectively, each of said first and said second timing signals having a duration substantially equal to said burst length; synchronism monitoring means responsive to said third timing signal and said delayed synchronizing bit for monitoring the synchronism of said local frame phase with said first frame phase for producing in response thereto an out of synchronism signal only when said local frame phase is out of synchronism with said first frame phase; fourth means connected to said resettable counting means and said synchronism monitoring means for putting said first means in said first mode only during presence of said first timing signal while said out of synchronism signal is absent and irrespective of states of said first through said third timing signals while said out of synchronism signal is present; and fifth means connected to said resettable counting means and said synchronism monitoring means for putting said second means in said second mode only during presence of said second timing signal while said out of synchronism signal is absent and out of said second mode irrespective of states of said first through said third timing signals while said out of synchronism signal is present.

Claim 10

A subscriber terminal as claimed in claim 8, wherein said synchronism monitoring means comprises a flip-flop responsive to said third timing signal and said delayed synchronizing bit for latching said delayed synchronizing bit only when said third preselected phase is in synchronism with said first frame phase for producing in response thereto said out of synchronism signal only when said delayed synchronizing bit is not latched.

Claim 11

A subscriber terminal as claimed in claim 9, wherein: said resettable counting means produces a first and a second counting means output signal, said first counting means output signal being a logic "0" for representing an active state of said first timing signal, said second counting means output signal being a logic "1" for representing an active state of said second timing signal; said synchronism monitoring means producing a monitoring means output signal being a logic "0" for representing an active state of said out of synchronism signal; said fourth means comprising: a two-input AND gate supplied with said first counting means output signal and said monitoring means output signal for producing in response thereto a first output signal; and means for supplying said first output signal to said first means, said first means being put in and out of said first mode when said first output signal is at logic "0" and logic "1" levels, respectively; said fifth means comprising: a two-input AND gate supplied with said second counting means output signal and said monitoring means output signal for producing in response thereto a second output signal; and means for supplying said second output signal to said second means, said second means being put in and out of said second mode when said second output signal is at logic "1" and logic "0" levels, respectively.

Claim 12

A subscriber terminal as claimed in claim 8, wherein said synchronism monitoring means comprises: means responsive to said third timing signal and each receive signal for producing a trigger signal only when said third preselected phase is out of synchronism with said first frame phase; and a monostable multivibrator responsive to said trigger signal for producing said out of synchronism signal during an interval of time equal to a product of said frame period and a predetermined natural number after said trigger signal is produced.

Claim 13

A subscriber terminal as claimed in claim 11, wherein: said resettable counting means produces a first and a second counting means output signal, said first counting means output signal being a logic "0" for representing an active state of said first timing signal, said second counting means output signal being a logic "1" for representing an active state of said second timing signal; said monostable multivibrator producing a monostable multivibrator output signal being a logic "0" for representing an active state of said out of synchronism signal; said fourth means comprising: a two-input AND gate supplied with said first counting means output signal and said monostable multivibrator output signal to produce a first output signal; and means for supplying said first output signal to said first means, said first means being put in and out of said first mode when said first output signal is at logic "0" and logic "1" levels, respectively; said fifth means comprising: a two-input AND gate supplied with said second counting means output signal and said monostable multivibrator output signal for producing in response thereto a second output signal; and means for supplying said second output signal to said second means, said second means being put in and out of said second mode when said second output signal is at logic "1" and logic "0" levels, respectively.

Claim 14

A subscriber terminal as claimed in claim 8, wherein, for a case in which said delayed synchronizing bit is at a logic "1" level: said resettable counting means produces a first, a second, and a third counting means output signal, said first counting means output signal being a logic "0" for representing an active state of said first timing signal, said second counting means output signal being a logic "1" for representing an active state of said second timing signal, said third timing means output signal being a logic "1" for representing an active state of said third timing signal and otherwise, respectively; said synchronism monitoring means comprising: a first flip-flop having a data, a clock, and a preset input terminal for latching the delayed synchronizing bit supplied to said data input terminal by the third counting means output signal supplied to said clock input terminal for producing in response thereto a first flip-flop output signal at logic "1" and logic "0" levels when said third preselected phase is in and out of synchronism with said first frame phase, respectively, said first flip-flop being preset by a preset input signal supplied to said preset input terminal during out of synchronism of said third preselected phase with said first frame phase thereby setting said first flip-flop output signal to a logic "1" level; a second flip-flop having a data, a clock, and a clear input terminal, said second flip-flop being cleared for producing a second flip-flop output signal at a logic "0" level when the first flip-flop output signal supplied to said clear input terminal is at a logic "0" level, said second flip-flop latching a logic "1" signal continuously supplied to said data input terminal for changing said second flip-flop output signal to a logic "1" level when the third counting means output signal supplied to said clock input terminal changes from a logic "1" level to a logic "0" level; and means for supplying the second flip-flop output signal at a logic "0" level to said preset input terminal as said preset input signal; said fourth means comprising: a single flip-flop having a data, a clock, and a clear input terminal, said single flip-flop being cleared to produce a single flip-flop output signal at a logic "0" level when the second flip-flop output signal supplied to said clear input terminal changes from a logic "1" level to a logic "0" level, said single flip-flop latching a logic "1" signal continuously supplied to said data input terminal for changing said single flip-flop output signal from a logic "0" level to a logic "1" level when the first counting means output signal supplied to said clock input terminal changes from a logic "0" level to a logic "1" level; a two-input AND gate supplied with said first counting means output signal and said single flip-flop output signal for producing in response thereto a first output signal; and means for supplying said first output signal to said first means, said first means being put in and out of said first mode when said first output signal is at logic "0" and logic "1" levels, respectively; said fifth means comprising: a two-input AND gate supplied with said second counting means output signal and said second flip-flop output signal for producing in response thereto a second output signal; and means for supplying said second output signal to said second means, said second means being put in and out of said second mode when said second output signal is at logic "1" and the logic "0" levels, respectively.

Claim 15

A subscriber terminal as claimed in claim 1, wherein the improvement further comprises each signal burst having a predetermined burst length shorter than a half of said frame period and comprising a burst synchronizing bit and a predetermined number of information bits, each receive signal comprising the synchronizing bit with a logic "1" level and the information bits at a predetermined bit rate and with a receive bit phase dependent on a predetermined bit phase, and wherein said third means comprises: clock producing means for producing local clocks at said predetermined bit rate and with said receive bit phase; resettable counting means repeatedly reset by a sequence of reset signals to a predetermined count representative of a local frame phase for counting said clocks from said predetermined count to successive counts representative of successive phases relative to said local frame phase to produce a first, a second, and an additional timing signal, each of said first, said second, and said additional timing signals being variable between a logic "1" level and a logic "0" level, said first timing signal changing from the logic "1" level to the logic "0" level and said second timing signal changing from the logic "0" level to the logic "1" level to indicate a first and a second preselected phase, respectively, relative to said local frame phase, each of the first timing signal of the logic "0" level and the second timing signal of the logic "1" level having a duration substantially equal to said burst length, said additional timing signal temporarily being a logic "1" level while said first timing signal is a logic "1" level; a two-input OR gate supplied with an OR gate input signal and said receive signals for producing in response thereto an OR gate output signal; a flip-flop having a data, a clock, and a clear input terminal supplied with said OR gate output signal, said clocks, and said additional timing signal, respectively, for producing in response thereto a true and an inverse output signal; means for supplying said true output signal to said OR gate as said OR gate input signal; a NAND gate supplied with said OR gate output signal and said inverse output signal to produce a NAND gate output signal; means for supplying said NAND gate output signal to said resettable counting means as each reset signal to synchronize said local frame phase to said first frame phase; and means for supplying said first and said second timing signals to said first and said second means, said first means being put in and out of said first mode when said first timing signal is at logic "0" and the logic "1" levels, respectively, said second means being put in and out of said second mode when said second timing signal is at logic "1" and logic "0" levels, respectively.

Claim 16

A subscriber terminal as claimed in claim 1, each signal burst having a predetermined burst length shorter than a half of said frame period and comprising a burst synchronizing bit and a predetermined number of information bits, each receive signal comprising the synchronizing bit with a logic "1" level and the information bits at a predetermined bit rate and with a receive bit phase dependent on a predetermined bit phase, wherein said third means comprises: clock producing means for producing local clocks at said predetermined bit rate and with said receive bit phase; resettable counting means repeatedly reset by a sequence of reset signals to a predetermined count representative of a local frame phase for counting said clocks from said predetermined count to successive counts representative of successive phases relative to said local frame phase to produce a first, a second, and an additional timing signal, each of said first, said second, and said additional timing signals being variable between the logic "1" level and a logic "0" level, said first timing signal turning from the logic "1" level to the logic "0" level and said second timing signal turning from the logic "0" to the logic "1" level to indicate a first and a second preselected phase relative to said local frame phase, respectively, each of the first timing signal of the logic "0" level and the second timing signal of the logic "1" level having a duration substantially equal to said burst length, said additional timing signal temporarily having the logic "1" level while said first timing signal has the logic "1" level; a two-input OR gate supplied with an OR gate input signal and said receive signals for producing in response thereto an OR gate output signal; a first two-input NAND gate supplied with a NAND gate input signal and said additional timing signal for producing in response thereto a first NAND gate output signal; a flip-flop having a data, a clock, and a clear input terminal supplied with said OR gate output signal, said clocks, and said first NAND gate output signal, respectively, to produce a true and an inverse output signal; means for supplying said true output signal to said OR gate an said first NAND gate as said OR gate input signal and said NAND gate input signal, respectively; a second two-input NAND gate supplied with said OR gate output signal and said inverse output signal for producing in response thereto a second NAND gate output signal; means for supplying said second NAND gate output signal to said resettable counting means as each reset signal to synchronize said local frame phase to said first frame phase; and means for supplying said first and said second timing signals to said first and said second means, said first means being put in and out of said first mode when said first timing signal is at logic "0" and the logic "1" levels, respectively, said second means being put in and out of said second mode when said second timing signal is at the logic "1" and the logic "0" levels, respectively.

Claim 17

A subscriber terminal as claimed in any one of claims 2 through 14 or 15, wherein said clock producing means comprises means responsive to said receive signals for producing said local clocks.

Claim 18

A subscriber terminal as claimed in any one of claims 2 through 14 or 15, wherein said clock producing means comprises: a local clock generator for generating higher rate clocks at a rate higher than said predetermined bit rate; a resettable counter for counting said higher rate clocks for producing in response thereto generated clocks substantially at said predetermined bit rate and with a local clock phase; and means for resetting said resettable counter to a preselected count by the higher rate clock generated for the first time after each extracted synchronizing bit is produced, thereby to synchronize said local clock phase to said receive bit phase.