Semiconductor device

Claim 2

In a semiconductor device containing at least one static induction transistor, said transistor including a source semiconductor region and a drain semiconductor region both having a first conductivity type and a low resistivity, a channel region having said first conductivity type and a high resistivity and a gate region having a second conductivity type opposite to said first conductivity type and having a low resistivity; said source and drain region being disposed to define a main current path therebetween through said channel region, said gate region being disposed to substantially control the potential of an intermediate semiconductor region in said current path, the improvement wherein: said intermediate semiconductor region is interposed in said current path contacting said source region, gate region and channel region, and is of said first conductivity type, and a resistivity higher than that of said channel region; and said transistor further includes: a first isolating insulator region disposed in contact with said gate region and disposed between said gate region and said drain region; and a second insulator region disposed to isolate said souce region from said gate region.

Claim 3

A semiconductor device containing at least one static induction transistor, said transistor including a source semiconductor region and a drain semiconductor region both having a first conductivity type and a low resistivity, a channel region having said first conductivity type and a high resistivity and a gate region having a second conductivity type opposite to said first conductivity type and having a low resistivity; said source and drain region being disposed to define a main current path therebetween through said channel region, said gate region being disposed to substantially control the potential of an intermediate semiconductor region in said current path, the improvement wherein: said an intermediate semiconductor region is interposed in said current path contacting said source region, gate region and channel region, and is of said second conductivity type and a high resistivity; and said transistor further includes: a first isolating insulator region disposed in contact with said gate region and disposed between said gate region and said drain region; and a second insulator region disposed to isolate said source region from said gate region.

Claim 4

A semiconductor device containing at least one static induction transistor, said transistor including a source semiconductor region and a drain semiconductor region both having a first conductivity type and a low resistivity, a channel region having said first conductivity type and a high resistivity and a gate region having a second conductivity type opposite to said first conductivity type and having a low resistivity; said source and drain region being disposed to define a main current path therebetween through said channel region, said gate region being disposed to substantially control the potential of an intermediate semiconductor region in said current path, the improvement wherein: said an intermediate semiconductor region is interposed in said current path contacting said source region, gate region and channel region, and is of said second conductivity type and a high resistivity; and said transistor further includes: a first isolating insulator region disposed in contact with said gate region and disposed between said gate region and said drain region; and a second insulator region disposed to isolate said source region from said gate region.

Claim 5

The device of claim 1 or 2 wherein said first insulator region is disposed in contact with said drain region.

Claim 6

A semiconductor device containing at least one static induction transistor, said transistor comprising: a source region having a first conductivity type and a low resistivity; an intermediate semiconductor region provided in contact with said source region and having a second conductivity type opposite to said first conductivity and having a high resistivity; a drain region having said first conductivity type and a low resistivity; a semiconductor region intervening between said intermediate region and said drain region in contact with both of them and having said first conductivity type and a high resistivity; an insulator film formed on one surface of said intermediate region; and a gate electrode provided on said insulator film.

Claim 7

A semiconductor device containing at least one static induction transistor, said transistor comprising: a source region having a first conductivity type and a low resistivity; an intermediate semiconductor region provided in contact with said source region and having a second conductivity type opposite to said first conductivity and having a high resistivity; a drain region having said first conductivity type and a low resistivity; a semiconductor region intervening between said intermediate region and said drain region in contact with both of them and having said first conductivity type and a high resistivity; an insulator film formed on one surface of said intermediate region; and a gate electrode provided on said insulator film.

Claim 8

A semiconductor device containing at least one static induction transistor, said transistor comprising: a source region having a first conductivity type and a low resistivity; an intermediate semiconductor region provided in contact with said source region and having a second conductivity type opposite to said first conductivity and a high resistivity; a drain region having said first conductivity type and a low resistivity; an intervening semiconductor region intervening between said intermediate region and said drain region in contact with both thereof, said intervening region having said first conductivity type and a high resistivity; a semi-insulating film formed on one surface of said intermediate region; a control electrode provided on said semi-insulating film.

Claim 9

A semiconductor device containing at least one static induction transistor, said transistor comprising: a source region having a first conductivity type and a low resistivity; an intermediate semiconductor region provided in contact with said source region and having a second conductivity type opposite to said first conductivity and a high resistivity; a drain region having said first conductivity type and a low resistivity; an intervening semiconductor region intervening between said intermediate region and said drain region in contact with both thereof, said intervening region having said first conductivity type and a high resistivity; a semi-insulating film formed on one surface of said intermediate region; a control electrode provided on said semi-insulating film.

Claim 10

A semiconductor device containing at least one static induction transistor, said transistor comprising: a main surface; a source region having a first conductivity type of a low resistivity, and being disposed to contact said main surface; a first intermediate semiconductor region having a second conductivity type opposite to said first conductivity type and having a high resistivity, and being disposed to contact with a portion of said source region; a second intermediate semiconductor region of said second conductivity type but having a resistivity lower than that of said first intermediate semiconductor region, said second intermediate semiconductor region being disposed to surround portions of said source region not in contact with said first intermediate region; a drain region of said first conductivity type, having a low resistivity; a semiconductor region intervening between at least said first intermediate semiconductor region and said drain region, contacting said first intermediate semiconductor, said drain region and having said first conductivity type and said high resistivity; a film, disposed to at least contact said first intermediate semiconductor region, comprising an insulating material; and a gate electrode contacting at least said film.

Claim 11

A semiconductor device containing at least one static induction transistor, said transistor comprising: a main surface; a source region having a first conductivity type of a low resistivity, and being disposed to contact said main surface; a first intermediate semiconductor region having a second conductivity type opposite to said first conductivity type and having a high resistivity, and being disposed to contact with a portion of said source region; a second intermediate semiconductor region of said second conductivity type but having a resistivity lower than that of said first intermediate semiconductor region, said second intermediate semiconductor region being disposed to surround portions of said source region not in contact with said first intermediate region; a drain region of said first conductivity type, having a low resistivity; a semiconductor region intervening between at least said first intermediate semiconductor region and said drain region, contacting said first intermediate semiconductor, said drain region and having said first conductivity type and said high resistivity; a film, disposed to at least contact said first intermediate semiconductor region, comprising an insulating material; and a gate electrode contacting at least said film.

Claim 12

The device of claim 4 or 6 wherein said film is formed of a material selected from the group consisting of SiO 2 , Si 3 N 4 , Al 2 O 3 , AlN and a mixture of them.

Claim 13

The device of claim 4 or 6 wherein said film comprises a multi-element insulating layer mixed with a conductivity enhancing element.

Claim 14

The device of claim 8 wherein said conductivity enhancing element is PbO.

Claim 15

The device of claim 6 wherein said film is formed of insulating material having a conductivity enhancing element mixed therewith.