US4404528A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output amplifier
Assignee: Toshiba Corp
•
Filing: 1981-09-11
•
Granted: 1983-09-13
•
Expires: 2001-09-11
Abstract
Abstract An output amplifier comprises an output transistor and a biasing transistor whose emitter is connected to the emitter of the output transistor. The polarity of the biasing transistor is the same as that of the output transistor. Resistors of small resistance are connected to the collector and base of the biasing transistor, respectively. The other ends of these resistors are connected to the base of the output transistor. When an input signal in the positive cycle is applied to the base of the output transistor, the circuit comprising the biasing transistor and the resistors operates as a resistance circuit. On the other hand, when no signal is applied to the base of the output transistor, or when a signal in the negative cycle is applied to the base of the output transistor, the circuit operates as a current mirror circuit. Therefore, when the output transistor is cut off, the biasing transistor is simultaneously cut off.
Inventors
- 👤 Hiroyasu Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:45
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/30; H03F3/3083; H03F3/3086; H03F3/3088; H03F1/00; H03F1/32; H03F1/3217; H03F3/3066
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
135 words
An output amplifier comprising: an output transistor; a biasing transistor whose emitter is connected to the emitter of said output transistor and whose polarity is the same as the polarity of said output transistor; a first resistor connected to the collector of said biasing transistor; and a second resistor connected to the base of said biasing transistor, the other end of said second resistor being connected to the other end of said first resistor, a node of said first and second resistors being connected to the base of said output transistor, and a signal being input at said node; whereby a circuit comprising said biasing transistor and said first and second resistors operates as a current mirror circuit when a small current is applied and as a resistance circuit when a large current is applied.
Claim 2
Dependent Claim
135 words
An output amplifier comprising: an output transistor; a biasing transistor whose emitter is connected to the emitter of said output transistor and whose polarity is the same as the polarity of said output transistor; a first resistor connected to the collector of said biasing transistor; and a second resistor connected to the base of said biasing transistor, the other end of said second resistor being connected to the other end of said first resistor, a node of said first and second resistors being connected to the base of said output transistor, and a signal being input at said node; whereby a circuit comprising said biasing transistor and said first and second resistors operates as a current mirror circuit when a small current is applied and as a resistance circuit when a large current is applied.
Claim 3
Dependent Claim
288 words
An SEPP power amplifier comprising: a first output transistor; a first biasing transistor whose emitter is connected to the emitter of said first output transistor and whose polarity is the same as the polarity of said first output transistor; a first resistor connected to the collector of said first biasing transistor; a second resistor connected to the base of said first biasing transistor, the other end of said second resistor being connected to the other end of said first resistor, a node of said first and second resistors being connected to the base of said first output transistor, and a first signal being input at said node; a second output transistor connected to said first output transistor so as to form an SEPP output circuit, an output being produced from a node of said first and second output transistor; a second biasing transistor whose emitter is connected to the emitter of said second output transistor and whose polarity is the same as that of said second output transistor; a third resistor connected to the collector of said second biasing transistor; and a fourth resistor connected to the base of said second biasing transistor, the other end of said fourth resistor being connected to the other end of said third resistor, a node thereof being connected to the base of said second output transistor, and a second signal of opposite phase to said first signal being input at said node; whereby a circuit comprising said first biasing transistor and said first and second resistors and a circuit comprising said second biasing transistor and said third and fourth resistors operate as current mirror circuits when a small current is applied and as resistance circuits when a large current is applied.
Claim 4
Dependent Claim
288 words
An SEPP power amplifier comprising: a first output transistor; a first biasing transistor whose emitter is connected to the emitter of said first output transistor and whose polarity is the same as the polarity of said first output transistor; a first resistor connected to the collector of said first biasing transistor; a second resistor connected to the base of said first biasing transistor, the other end of said second resistor being connected to the other end of said first resistor, a node of said first and second resistors being connected to the base of said first output transistor, and a first signal being input at said node; a second output transistor connected to said first output transistor so as to form an SEPP output circuit, an output being produced from a node of said first and second output transistor; a second biasing transistor whose emitter is connected to the emitter of said second output transistor and whose polarity is the same as that of said second output transistor; a third resistor connected to the collector of said second biasing transistor; and a fourth resistor connected to the base of said second biasing transistor, the other end of said fourth resistor being connected to the other end of said third resistor, a node thereof being connected to the base of said second output transistor, and a second signal of opposite phase to said first signal being input at said node; whereby a circuit comprising said first biasing transistor and said first and second resistors and a circuit comprising said second biasing transistor and said third and fourth resistors operate as current mirror circuits when a small current is applied and as resistance circuits when a large current is applied.
Claim 5
Dependent Claim
246 words
The SEPP power amplifier according to claim 2, wherein said first and second output transistors are connected at their bases to first and second amplifying circuits; said first amplifying circuit comprising a third output transistor whose collector is connected to the base of said first output transistor; a third biasing transistor whose emitter is connected to the emitter of said third output transistor and whose polarity is the same as the polarity of said third output transistor; a fifth resistor connected to the collector of said third biasing transistor; a sixth resistor connected to the base of said third biasing transistor, the other end of said sixth resistor being connected to the other end of said fifth resistor, a node of said fifth and sixth resistors being connected to the base of said third output transistor; said second amplifying circuit comprising a fourth output transistor whose collector is connected to the base of said second output transistor; a fourth biasing transistor whose emitter is connected to the emitter of said fourth output transistor and whose polarity is the same as the polarity of said fourth output transistor; a seventh resistor connected to the collector of said fourth biasing transistor; an eighth resistor connected to the base of said fourth biasing transistor, the other end of said eighth resistor being connected to the other end of said seventh resistor, a node of said seventh and eighth resistors being connected to the base of said fourth output transistor.
References Cited (Backward Citations)
US3534279A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-12 | 1987-03-14 | 1987-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-12 | 1991-03-14 | 1991-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-12 | 1995-03-14 | 1995-09-13 | $7700.00 | Window Closed / Lapsed |