US4403245A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and circuit for time-correction of digital switching signals
Assignee: Robert Bosch GmbH
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Filing: 1981-10-01
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Granted: 1983-09-06
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Expires: 2001-10-01
Abstract
Abstract A time correction value for each digital switching signal is determined and a set of switching control signals is formed which produce a progressive switching of the digital signal as a function of the time correction value. Each time correction value is stored until the following digital switching signal. The method improves chroma keying in digital color television systems.
Inventors
- 👤 Gerhard Wischermann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:18
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/74; H04N9/75
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
189 words
A method for the time-correction of digital switching signals which can occur only at discrete times as a consequence of the sampling process by which the digital signal to be switched is derived and which is therefore delayed relative to its desired time of occurrence, the method comprising deriving a time correction signal whose value is dependent upon the amount by which the digital switching signal is delayed relative to the desired time, and generating a set of control signals at the sampling frequency of the digital signal and having values determined by the value of the time correction signal, the control signals collectively constituting the time-corrected switching signal and being effective to produce a progressive switching of the digital signal over a plurality of sampling periods, the time correction signal for each digital switching signal being stored and, immediately upon the occurrence of the next following digital switching signal, being replaced in storage by the time correction signal corresponding to that next digital switching signal whereby a fresh set of control signals are produced irrespective of whether the set corresponding to the previous digital switching signal are completed.
Claim 2
Independent Claim
189 words
A method for the time-correction of digital switching signals which can occur only at discrete times as a consequence of the sampling process by which the digital signal to be switched is derived and which is therefore delayed relative to its desired time of occurrence, the method comprising deriving a time correction signal whose value is dependent upon the amount by which the digital switching signal is delayed relative to the desired time, and generating a set of control signals at the sampling frequency of the digital signal and having values determined by the value of the time correction signal, the control signals collectively constituting the time-corrected switching signal and being effective to produce a progressive switching of the digital signal over a plurality of sampling periods, the time correction signal for each digital switching signal being stored and, immediately upon the occurrence of the next following digital switching signal, being replaced in storage by the time correction signal corresponding to that next digital switching signal whereby a fresh set of control signals are produced irrespective of whether the set corresponding to the previous digital switching signal are completed.
Claim 3
Dependent Claim
27 words
Method as claimed in claim 1, including the step of producing the corrected digital switching signals by a non-recursive digital filter controllable by said time correction signal.
Claim 4
Dependent Claim
151 words
A circuit arrangement for time correction of digital switching signals comprising a series of delay elements each with a delay of one sampling period, the digital switching signals being fed to a first delay element of the series, a plurality of multiplier stages, the input of each delay element and the output of the last delay element being connected each to one input of a respective multiplier stage, a programmable read-only memory having a plurality of outputs connected each to a further input of a respective multiplier stage, the input of the programmable read-out memory being supplied with the current time correction signal via a sample and hold circuit (31) to which is fed a sampling signal upon the occurrence of each digital switching signal, and an adding circuit the inputs of which are connected to the outputs of the multiplier stages, the output of the adder forming the control signals.
Claim 5
Dependent Claim
151 words
A circuit arrangement for time correction of digital switching signals comprising a series of delay elements each with a delay of one sampling period, the digital switching signals being fed to a first delay element of the series, a plurality of multiplier stages, the input of each delay element and the output of the last delay element being connected each to one input of a respective multiplier stage, a programmable read-only memory having a plurality of outputs connected each to a further input of a respective multiplier stage, the input of the programmable read-out memory being supplied with the current time correction signal via a sample and hold circuit (31) to which is fed a sampling signal upon the occurrence of each digital switching signal, and an adding circuit the inputs of which are connected to the outputs of the multiplier stages, the output of the adder forming the control signals.
Claim 6
Dependent Claim
101 words
A circuit arrangement for time correction of digital switching signals comprising a series of delay elements each with a delay of one sampling period, the digital switching signals being fed to a first delay element of the series, a programmable read-only memory having a plurality of inputs connected respectively to the input of each delay element and to the output of the last delay element, and a further input of the programmable read-only memory being supplied with the current time correction signal via a sample-and-hold circuit to which is fed a sampling signal upon the occurrence of each digital switching signal.
Claim 7
Dependent Claim
101 words
A circuit arrangement for time correction of digital switching signals comprising a series of delay elements each with a delay of one sampling period, the digital switching signals being fed to a first delay element of the series, a programmable read-only memory having a plurality of inputs connected respectively to the input of each delay element and to the output of the last delay element, and a further input of the programmable read-only memory being supplied with the current time correction signal via a sample-and-hold circuit to which is fed a sampling signal upon the occurrence of each digital switching signal.
Claim 8
Dependent Claim
41 words
A circuit arrangement as claimed in claim 3, wherein for providing the sampling signal the digital switching signals are fed on the one hand directly and on the other hand via a delay circuit to the inputs of an EX-OR circuit.
Claim 9
Dependent Claim
41 words
A circuit arrangement as claimed in claim 4, wherein for providing the sampling signal the digital switching signals are fed on the one hand directly and on the other hand via a delay circuit to the inputs of an EX-OR circuit.
Claim 10
Dependent Claim
25 words
A circuit arrangement according to claim 3, including a non-recursive digital filter controllable by said time correction signal fo producing the corrected digital switching signals.
Claim 11
Dependent Claim
25 words
A circuit arrangement according to claim 4, including a non-recursive digital filter controllable by said time correction signal for producing the corrected digital switching signals.
Claim 12
Dependent Claim
25 words
A circuit arrangement according to claim 5, including a non-recursive digital filter controllable by said time correction signal for producing the corrected digital switching signals.
Claim 13
Dependent Claim
25 words
A circuit arrangement according to claim 6, including a non-recursive digital filter controllable by said time correction signal for producing the corrected digital switching signals.
References Cited (Backward Citations)
US4109278A
Cited
US4122490A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-09-05 | 1987-03-07 | 1987-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-09-05 | 1991-03-07 | 1991-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-09-05 | 1995-03-07 | 1995-09-06 | $7700.00 | Window Closed / Lapsed |