Abstract A signal processing system comprises an analogue shift register of the charge coupled type (24) fed from a sampling device (22) and controlled by a clock arrangement (26) having three independent clocks (26A, 26B and 26C). Clock (26A) determines the sampling rate of sampling device (22) and the rate at which such samples are clocked into register (24). Clock 26C determines the rate at which stored samples are clocked out of the register (24). Clocks 26A and 26C operate in the MHz range. Clock 26B operates in the KHz range and dictates the sample storage interval and clocks the stored samples through a number of storage sites in register (24) during the storage interval to reduce the adverse effects of geometrical and other inhomogeneities of the individual register sites on the individual stored samples.
Inventors
👤 Peter J. Berry
👤 John Y. C. Montgomery
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-26 23:03
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/04
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
103 words
A signal processing system comprising an analogue shift register of the charge coupled type, clock means arranged for clocking samples of an input signal into the CCD shift register, for determining the storage time of the signal in the CCD shift register, and for clocking the signal out of the CCD shift register, wherein the number of samples of the input signal is less than the number of sites in the CCD shift register and during the storage time the clock means is arranged to clock the stored samples through at least some of the register sites unfilled during the clocking in period.
Claim 2
Dependent Claim
103 words
A signal processing system comprising an analogue shift register of the charge coupled type, clock means arranged for clocking samples of an input signal into the CCD shift register, for determining the storage time of the signal in the CCD shift register, and for clocking the signal out of the CCD shift register, wherein the number of samples of the input signal is less than the number of sites in the CCD shift register and during the storage time the clock means is arranged to clock the stored samples through at least some of the register sites unfilled during the clocking in period.
Claim 3
Dependent Claim
40 words
A system as claimed in claim 1, wherein the clock means is arranged to clock the stored samples during the storage time at a rate substantially less than for clocking the samples into or out of the CCD shift register.
Claim 4
Dependent Claim
65 words
A system as claimed in claim 1, wherein the clock means comprises three separate clocks, the first of which controls the rate of samples clocked into the CCD shift register, the second of which controls the rate of samples clocked through the shift register during the storage time, and the third of which controls the rate of samples clocked out of the CCD shift register.
Claim 5
Dependent Claim
31 words
A thermal imager comprising a scanner and a radiation detector the output of which detector is fed to a video device via a signal processing system as claimed in claim 1.