Signal switching matrix

Claim 2

An M by N signal switching matrix for coupling various ones of N input lines to various ones of M output lines comprising in combination: N single-pole, M-throw input switches coupled to said N input lines where each of said switches has M outputs; M N-throw, single-pole output switches coupled to said M output lines where each of said output switches has N inputs; M*N connections between respective ones of the M outputs of the N input switches and respective ones of N inputs to the M output switches where M and N are integers, M<=>N and * is the multiplication symbol.

Claim 3

The combination as set forth in claim 1 wherein each said input switch comprises a plurality of single-pole two-throw switches positioned to connect the input thereto to any one of the M outputs thereof.

Claim 4

The combination as set forth in claim 1 wherein each output switch comprises a plurality of two-throw single-pole switches arranged to connect the N inputs thereto to an output line thereof.

Claim 5

The combination as set forth in claim 2 wherein each output switch comprises a plurality of two-throw single-pole switches arranged to connect the N inputs thereto to an output line thereof.

Claim 6

The combination as set forth in claim 3 wherein each said input switch comprises a plurality of single-pole two-throw switches arranged to connect the input thereto to any one of the M outputs thereof.

Claim 7

The combination as set forth in either claim 3 or 4 wherein said two-throw single-pole switch comprises a pair of dual-gate FET transistors.

Claim 8

The combination as set forth in claim 6 wherein the input of said single-pole two-throw switch is connected to the signal gates of said two transistors, the source and drain of one of said transistors coupled between circuit ground and the output of the switch and the source and drain of the other transistor are connected between circuit ground and the other output of the said switch.

Claim 9

The combination as set forth in claim 7 wherein the control gates of said first transistors are coupled to receive mutually exclusive control signals such that only one of the transistors is enabled at a time.

Claim 10

The combination as set forth in claim 8 wherein the source and drains of said two transistors are coupled together respectively and wherein said sources and drains are connected between circuit ground and the output of said switch and wherein the inputs to said switch are coupled to the signal gates respectively of said two transistors.

Claim 11

The combination as set forth in claim 9 wherein the mutually exclusive control signals are coupled to the control gates of said two transistors such that only one transistor is enabled at a time to pass the signal applied to its signal gate to the switch output.

Claim 12

The combination as set forth in either claim 2 or claim 5 wherein said single-pole two-throw switch comprises first and second pairs of dual-gate FET transistors, each transistor having a signal input gate, a control input gate, a source and a drain.

Claim 13

The combination as set forth in claim 11 wherein the sources and drains of said first pair of transistors are coupled between circuit ground and one of the switch outputs, wherein the sources and drains of said second pair of transistors are coupled respectively together between the circuit ground and a second output of said switch, wherein the signal gates of all four of said first and second pair of transistors are coupled together to the input of said switch wherein the control gates of said first pair of transistors are coupled together and wherein the control gates of said second pair of transistors are coupled together and coupled respectively to receive mutually exclusive control signals thereat such that only one pair of transistors is conductive at one time to pass the input signal applied thereto to the output thereof associated with the conductive pair of transistors.