US4397031A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Time delay computer
Assignee: Individual
•
Filing: 1980-12-04
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Granted: 1983-08-02
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Expires: 2000-12-04
Abstract
Abstract The time of arrival of a constant speed moving object at a given location is calculated from data representing the time of arrival of the object at two preceeding locations and the relative physical distances between the three locations. An up-down counter counts up at a fixed frequency f 1 during the time interval of the object's transversal of the distance between the first two locations and counts down at a pre-selected frequency f 2 thereafter. The preselected frequency f 2 is a function of the distances between locations and the fixed frequency f 1 . When the counter counts down to zero it produces an output pulse that occurs at the time the object reaches the given location. Operation of the time delay computer is independent of object speed.
Inventors
- 👤 Paul A. Weber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:54
CPC Classifications
G; G04; G04F; G04F10/00; G04F1/00; G04F1/005
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
299 words
A time delay computer means comprising: an up-down counter means, count up actuating means initiating count up from zero operation of said up-down counter at a first fixed frequency f 1 in response to a first input signal, said count up actuating means comprising a first flip-flop means receiving said first input signal, a fixed frequency oscillator means generating a signal of frequency f 1 , and a first AND gate means, said first AND gate means receiving the output of said fixed frequency oscillator means and actuating count-up operation of said up-down counter in response to an enabling signal from said flip-flop means, and count down actuating means disabling said count up actuating means and initiating count down operation of said up down counter means at a second pre-selected frequency f 2 in response to a subsequently received second input signal, there being a pre-selected ratio of the time interval between said first and second input signals and the time interval between said second input signal and an output signal generated by the said up-down counter means, said ratio being a function of said second pre-selected frequency f 2 , said up-down counter means further generating a count down actuating means disabling signal when the counter reaches zero, said count down actuating means comprising, a second flip flop means receiving said second input signal and said count down actuating means disabling signal and providing a disabling signal to said first flip flop means, a variable frequency oscillator means generating a signal of frequency f 2 , and a second AND gate means, said second AND gate means receiving the output of said variable frequency oscillator means and actuating count down operation of said up-down counter means in response to an enabling signal from said second flip flop means.
Claim 2
Dependent Claim
299 words
A time delay computer means comprising: an up-down counter means, count up actuating means initiating count up from zero operation of said up-down counter at a first fixed frequency f 1 in response to a first input signal, said count up actuating means comprising a first flip-flop means receiving said first input signal, a fixed frequency oscillator means generating a signal of frequency f 1 , and a first AND gate means, said first AND gate means receiving the output of said fixed frequency oscillator means and actuating count-up operation of said up-down counter in response to an enabling signal from said flip-flop means, and count down actuating means disabling said count up actuating means and initiating count down operation of said up down counter means at a second pre-selected frequency f 2 in response to a subsequently received second input signal, there being a pre-selected ratio of the time interval between said first and second input signals and the time interval between said second input signal and an output signal generated by the said up-down counter means, said ratio being a function of said second pre-selected frequency f 2 , said up-down counter means further generating a count down actuating means disabling signal when the counter reaches zero, said count down actuating means comprising, a second flip flop means receiving said second input signal and said count down actuating means disabling signal and providing a disabling signal to said first flip flop means, a variable frequency oscillator means generating a signal of frequency f 2 , and a second AND gate means, said second AND gate means receiving the output of said variable frequency oscillator means and actuating count down operation of said up-down counter means in response to an enabling signal from said second flip flop means.
Claim 3
Dependent Claim
94 words
A time delay computer means as defined in claim 1 wherein said first input signal is derived from a first sensor means, said second input signal is derived from a second sensor means, and said output signal controls a recorder means, said first and second sensor means and said recorder means being physically located in order along a straight line, said second sensor means being positioned between said first sensor means and said recorder means at a distance d 1 from said first sensor means and a distance d 2 from said recorder means.
Claim 4
Dependent Claim
31 words
A time delay computer means as defined in claim 2 wherein the frequency f 2 of said variable frequency oscillator means is f 2 =d 1 /d 2 f 1 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-01 | 1987-01-31 | 1987-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-01 | 1991-01-31 | 1991-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-01 | 1995-01-31 | 1995-08-02 | $7700.00 | Window Closed / Lapsed |