Controlled ram signal processor

Claim 2

A digital look-up table signal processing system comprising: a first high-speed RAM having addresses and producing at output terminals data representative of the contents of the accessed address selected by an incoming signal in accordance with a composite transfer function; a plurality of sources of control signals for determining components of said composite transfer function; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading said RAM with said new contents.

Claim 3

A system as claimed in claim 1, further comprising a second RAM, means for switching said incoming signal between said RAMs, and wherein said means for loading loads only that one of said RAMs not processing said incoming signal.

Claim 4

A system as claimed in claim 1, further comprising second and third RAMs, each of said RAMs coupled in a signal processing channel respectively, all RAMs being loaded by said means for loading.

Claim 5

A system as claimed in claim 3, wherein said channels comprise signals representing red, green and blue color component signals of a television signal.

Claim 6

A system as claimed in claim 1, wherein said sources of control signals each comprises a digital shaft encoder.

Claim 7

A system as claimed in claim 1, wherein said sources of control signals controls at least one of gain, pedestal, and gamma functions.

Claim 8

A system as claimed in claim 1, wherein said means for obtaining comprises a means for calculating said new contents.

Claim 9

A system as claimed in claim 7, wherein said means for calculating comprises circuitry coupled together in accordance with said algorithm.

Claim 10

A system as claimed in claim 7, wherein said means for calculating comprises a ROM means for storing said algorithm and a microprocessor coupled to said ROM means.

Claim 11

A system as claimed in claim 8, wherein said means for loading comprises an address generator having an input means for receiving a load clock and an output coupled to said RAM.

Claim 12

A system as claimed in claim 1, wherein said means for loading comprises a microprocessor coupled to said RAM.

Claim 14

A system as claimed in claim 1, wherein said means for obtaining comprises means for storing at least a portion of said new contents.

Claim 15

A digital look-up table signal processing system comprising: first and second high-speed RAMs each having addresses and producing at output terminals data representative of the contents of the accessed address selected for an incoming signal; means for switching said incoming signal between said RAMs; a source of control signals; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading that one of said RAMs not processing said incoming signal with said new contents.

Claim 16

A digital look-up table signal processing system comprising: first and second high-speed RAMs each having addresses and producing at output terminals data representative of the contents of the accessed address selected for an incoming signal; means for switching said incoming signal between said RAMs; a source of control signals; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading that one of said RAMs not processing said incoming signal with said new contents.

Claim 17

A digital look-up table signal processing system comprising: first, second and third high-speed RAMs, each of said RAMs coupled in a signal processing channel respectively and having addresses and producing at output terminals data representative of the contents of the accessed address selected by incoming signals; a source of control signals; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading all of said RAMs with said new contents.

Claim 18

A digital look-up table signal processing system comprising: first, second and third high-speed RAMs, each of said RAMs coupled in a signal processing channel respectively and having addresses and producing at output terminals data representative of the contents of the accessed address selected by incoming signals; a source of control signals; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading all of said RAMs with said new contents.

Claim 19

A digital look-up table signal processing system comprising: a first high-speed RAM having addresses and producing at output terminals data representative of the contents of the accessed address selected by an incoming signal; a source of control signals for controlling at least one of gain, pedestal, and gamma functions; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading said RAM with said new contents.

Claim 20

A digital look-up table signal processing system comprising: a first high-speed RAM having addresses and producing at output terminals data representative of the contents of the accessed address selected by an incoming signal; a source of control signals for controlling at least one of gain, pedestal, and gamma functions; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading said RAM with said new contents.

Claim 21

A digital look-up table signal processing system comprising: a first high-speed RAM having addresses and producing at output terminals data representative of the contents of the accessed address selected by an incoming digital video signal having a blanking interval; a source of control signals; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading said RAM wiith said new contents only during a blanking interval.

Claim 22

A digital look-up table signal processing system comprising: a first high-speed RAM having addresses and producing at output terminals data representative of the contents of the accessed address selected by an incoming digital video signal having a blanking interval; a source of control signals; means for obtaining from said control signals appropriate new contents for said addresses according to a predetermined algorithm; and means for loading said RAM wiith said new contents only during a blanking interval.

Claim 23

A digital video signal translating system comprising: a digital video signal path including a random access memory operable in first and second modes, and having address inputs responsive to an input digital video signal, and outputs for reproducing stored digital signals representative of said input digital video signal modified by a given transfer function when said memory is operated in said first mode, and operable in said second mode for loading applied digital signals into said memory; means for generating a control signal representative of the desired transfer function of said signal path; means responsive to said control signal for generating a table of digital signals for said random access memory; means, coupled to said generating means, for storing said table of digital signals; and means, coupled between said storing means and said random access memory, for loading said table of digital signals into said random access memory during a vertical retrace interval of said digital video signal.

Claim 24

A digital video signal translating system comprising: a digital video signal path including a random access memory operable in first and second modes, and having address inputs responsive to an input digital video signal, and outputs for reproducing stored digital signals representative of said input digital video signal modified by a given transfer function when said memory is operated in said first mode, and operable in said second mode for loading applied digital signals into said memory; means for generating a control signal representative of the desired transfer function of said signal path; means responsive to said control signal for generating a table of digital signals for said random access memory; means, coupled to said generating means, for storing said table of digital signals; and means, coupled between said storing means and said random access memory, for loading said table of digital signals into said random access memory during a vertical retrace interval of said digital video signal.

Claim 25

A digital video signal translation system comprising: a plurality of video signal paths, each including a random access memory operable in first and second modes, and having address inputs responsive to a respective input digital video signal, and signal outputs for reproducing data words stored in addressed memory locations, said data words being representative of said respective input digital video signal modified by a given transfer function, when said memory is operated in said first mode, and operable in said second mode for loading applied digital data words into said memory locations; means for generating a control signal representative of the desired transfer function of a selected one of said digital video signal paths; means responsive to said control signal for generating a table of digital data words; means, coupled to said generating means, for storing said table of digital data words; a data bus coupled between said storing means and said random access memories; and means for controllably loading said stored table of digital data words into said memory locations of said random access memory of said selected video signal path when said random access memory of said selected path is operating in said second mode.

Claim 26

A digital video signal translation system comprising: a plurality of video signal paths, each including a random access memory operable in first and second modes, and having address inputs responsive to a respective input digital video signal, and signal outputs for reproducing data words stored in addressed memory locations, said data words being representative of said respective input digital video signal modified by a given transfer function, when said memory is operated in said first mode, and operable in said second mode for loading applied digital data words into said memory locations; means for generating a control signal representative of the desired transfer function of a selected one of said digital video signal paths; means responsive to said control signal for generating a table of digital data words; means, coupled to said generating means, for storing said table of digital data words; a data bus coupled between said storing means and said random access memories; and means for controllably loading said stored table of digital data words into said memory locations of said random access memory of said selected video signal path when said random access memory of said selected path is operating in said second mode.