Coded security switch

Claim 2

For use in an alarm system in which a security switch is monitored to denote the transition state thereof, a circuit comprising: first gate means including a timing circuit coupled directly to said switch and operative to provide a start signal in response to each switch transition from an open to a closed state and from a closed to an open state and for a time interval determined by the timing circuit; first means coupled directly to said switch and operative to provide a logic level indicative of the open and closed states of said switch; transmission means including: encoder means operative to provide an output code in response to said logic level of the open and closed states of said switch; a transmitter operative in response to said output code and to said start signal to provide a coded signal for transmission along a communications path and representative of the transition states of said switch for each said switch transition.

Claim 3

The circuit of claim 1 wherein said transmission means is operative to provide said coded signal for a predetermined duration specified by the timing circuit.

Claim 4

The circuit of claim 1 including timer means operative to provide a test pulse to said encoder means to cause the transmission of a coded signal representing a test condition.

Claim 5

The circuit of claim 3 including circuit means operative to monitor the voltage of a battery source and to provide a low battery signal to said encoder means to cause the transition of a coded signal representing such low battery condition.

Claim 6

The circuit of claim 1 including timer means operative to provide a test pulse to said encoder means at a predetermined time intervals to cause the transmission of a coded signal representing a test condition.

Claim 7

The circuit of claim 5 wherein said timer means provides the test pulse to a start terminal of the encoder means thereby to turn on the encoder means, and to a test terminal of the encoder means thereby to produce the coded signal representing a test condition.

Claim 8

For use in an alarm system in which a security switch is monitored to denote the transition state thereof, a circuit comprising: first gate means including a timing circuit coupled directly to said switch and operative to provide a start signal in response to each switch transition from an open to a closed state and from a closed to an open state and for a time interval determined by the timing circuit; first means coupled directly to said switch and operative to provide a logic level indicative of the open and closed states of said switch; a programmable encoder operative to receive said start signal from said first gate means and said logic level from said first means and to provide an output code for the duration of the timing interval and representative of the transition state of said switch; and transmitter means operative in response to said output code and for a time interval determined by said start signal to provide a coded signal of a form for transmission along an intended communications path.

Claim 9

For use in an alarm system in which a security switch is monitored to denote the transition state thereof, a circuit comprising: first gate means including a timing circuit coupled directly to said switch and operative to provide a start signal in response to each switch transition from an open to a closed state and from a closed to an open state and for a time interval determined by the timing circuit; first means coupled directly to said switch and operative to provide a logic level indicative of the open and closed states of said switch; a programmable encoder operative to receive said start signal from said first gate means and said logic level from said first means and to provide an output code for the duration of the timing interval and representative of the transition state of said switch; and transmitter means operative in response to said output code and for a time interval determined by said start signal to provide a coded signal of a form for transmission along an intended communications path.

Claim 10

The circuit of claim 7 wherein said switch is a single pole, single throw switch; and wherein said first gate means includes: a first exclusive OR gate which provides a first logic level output in response to a switch transition; a second exclusive OR gate which provides a predetermined logic level output in response to the output of the first exclusive OR gate; and a timing circuit coupling the first exclusive OR gate to the second exclusive OR gate and operative in response to said first logic level output to cause said second exclusive OR gate to change state, the output of said second exclusive OR gate being said start signal.

Claim 11

The circuit of claim 8 wherein said first means derives the logic level indicative of the open and closed states of the switch from a source of reference potential.

Claim 12

The circuit of claim 9 further including circuit means operative to monitor the voltage of a battery source and to provide a low battery signal to said encoder, comprising: circuit means for providing a low battery signal when the battery voltage falls below a predetermined reference voltage; and gate means operative in response to the low battery signal to provide an input signal to the encoder to cause provision of an output code denoting the low battery condition.

Claim 13

The circuit of claim 7 wherein said switch is a single pole, single throw switch; and wherein said first gate means includes: a first inverter operative to provide a predetermined logic level output in response to one switch transition; a second inverter operative to provide said start signal in response to an opposite switch transition; a third inverter operative to provide said start signal in response to the output from said first inverter; a first timing circuit coupling the first inverter to the third inverter and operative to determine the duration of the start signal provided by the third inverter; a second timing circuit coupling the switch to the second inverter and operative to determine the duration of the start signal provided by the second inverter.

Claim 14

The circuit of claim 11 wherein said first means includes an inverter coupled to the output of said first inverter and operative to provide said logic level indicative of the open and closed states of the switch.

Claim 15

The circuit of claim 7 wherein the programmable encoder includes a start terminal to which said start signal from said first gate means is applied to enable the encoder, and a data terminal to which said logic level from said first means is applied to cause generation of the coded signal representative of the transition state of said switch.

Claim 16

An alarm system in which at least one security switch is monitored to denote the states thereof, comprising: first gate means including a timing circuit coupled directly to said switch and operative to provide a start signal in response to each switch transition from an open to a closed state and from a closed to an open state and for a time interval determined by the timing circuit; first means coupled directly to said switch and operative to provide a logic level indicative of the open and closed states of said switch; transmission means including: encoder means operative to provide an output code in response to said logic level of the open and closed states of said switch and for the duration of the timing interval; a transmitter operative in response to said output code and to said start signal to provide a coded signal for transmission along a communications path and representative of the transition states of said switch for each said switch transition; receiver means operative to receive the coded signal from said transmitter means and to demodulate the received signal; a decoder operative to decode the demodulated signal; and means for indicating alarm status.

Claim 17

An alarm system in which at least one security switch is monitored to denote the states thereof, comprising: first gate means including a timing circuit coupled directly to said switch and operative to provide a start signal in response to each switch transition from an open to a closed state and from a closed to an open state and for a time interval determined by the timing circuit; first means coupled directly to said switch and operative to provide a logic level indicative of the open and closed states of said switch; transmission means including: encoder means operative to provide an output code in response to said logic level of the open and closed states of said switch and for the duration of the timing interval; a transmitter operative in response to said output code and to said start signal to provide a coded signal for transmission along a communications path and representative of the transition states of said switch for each said switch transition; receiver means operative to receive the coded signal from said transmitter means and to demodulate the received signal; a decoder operative to decode the demodulated signal; and means for indicating alarm status.

Claim 18

The system of claim 14 wherein said means for indicating alarm status includes: counter means operative in response to signals from said decoder to provide an output count which denotes the number of monitored switches which are in an alarm state; and display means for indicating such alarm state.