US4396891A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gain control circuit
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1980-02-20
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Granted: 1983-08-02
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Expires: 2000-02-20
Abstract
Abstract A gain control circuit includes at least a first (T1, T2) and a second (T3, T4) transistor differential amplifier the input circuits of which are connected in parallel to a signal voltage source. The gain control is performed by distributing a constant current (Is) between these differential amplifiers as a function of a control quantity (Uc) for setting the transconductance of the stages in a complementary way. The two differential amplifiers are provided with negative feed back (F, R1, R2, R3) but with different feed back factors. As the transistors in the differential amplifiers carrying signals of the same phase are interconnected the output signal from the automatic gain control circuit will consist of a superposition of the output signals of the two differential amplifiers.
Inventors
- 👤 Jan H. Johansson
- 👤 Bengt O. Berg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:45
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0017; H03G1/0023
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
A gain control circuit comprising: first and second transistor differential amplifiers, each of said amplifiers having an input terminal means, output terminal means and common terminal means; means for applying an input signal to be amplified in parallel to each of said input terminal means; means for applying an operating current through said differential amplifiers via said output terminal means and said common terminal means, said applying means comprising signal amplifying means having an input terminal means, an output terminal means and a common terminal means, a constant current source connected to said common terminal means, means for connecting said output terminal means simultaneously to the common terminals of said differential amplifiers, and means for applying a continuously variable control signal to the input terminal means of said signal amplifying means negative feedback means connecting said output terminal means of said differential amplifiers to said input terminal means of said differential amplifiers, said negative feedback means being so dimentioned that said differential amplifiers together with said negative feedback network have different loop gains for the same current passing through their common terminals.
Claim 2
Dependent Claim
182 words
A gain control circuit comprising: first and second transistor differential amplifiers, each of said amplifiers having an input terminal means, output terminal means and common terminal means; means for applying an input signal to be amplified in parallel to each of said input terminal means; means for applying an operating current through said differential amplifiers via said output terminal means and said common terminal means, said applying means comprising signal amplifying means having an input terminal means, an output terminal means and a common terminal means, a constant current source connected to said common terminal means, means for connecting said output terminal means simultaneously to the common terminals of said differential amplifiers, and means for applying a continuously variable control signal to the input terminal means of said signal amplifying means negative feedback means connecting said output terminal means of said differential amplifiers to said input terminal means of said differential amplifiers, said negative feedback means being so dimentioned that said differential amplifiers together with said negative feedback network have different loop gains for the same current passing through their common terminals.
Claim 3
Dependent Claim
40 words
The gain control circuit of claim 1 further comprising output amplifier means having input circuit means connected to the output terminal means of said differential amplifiers and output circuit means connected to the input terminal means of said differential amplifiers.
Claim 4
Dependent Claim
23 words
The gain control circuit of claim 2 wherein said input circuit means, said output circuit means and said negative feedback means are balanced.
Claim 5
Dependent Claim
16 words
The gain control circuit of claim 1 wherein said signal amplifying means is a differential amplifier.
References Cited (Backward Citations)
US3452289A
Cited
FR2291642A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-01 | 1987-01-31 | 1987-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-01 | 1991-01-31 | 1991-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-01 | 1995-01-31 | 1995-08-02 | $7700.00 | Window Closed / Lapsed |