US4394702A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power failure detection and control circuit
Assignee: Unisys Corp
•
Filing: 1980-11-10
•
Granted: 1983-07-19
•
Expires: 2000-11-10
Abstract
Abstract A circuit is provided for detecting a low power condition which is undesirable and effectively turns off a computer system to prevent incorrect operation thereof. The circuit does not turn on the computer system until the correct power condition is achieved. The circuit is also sensitive to the power condition to establish the time duration permissible for causing the computer system to be turned off.
Inventors
- 👤 Guy Boothe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:23
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/30; H; H02; H02H; H02H3/00; H02H3/24
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
134 words
A circuit for detecting the condition of a power source comprising, a first pulse circuit (1, OS1) for selectively generating pulses (D) of a first time period and frequency as a function of the signal (C) supplied thereto from said power source, a second pulse circuit (OS2) for selectively generating pulses (E) of a second time period and frequency as a function of the pulses (D) supplied thereto by said first pulse circuit, said second pulse circuit selectively supplying pulses to said first pulse circuit to effectively disable said first pulse circuit, and reset circuit means (2, etc) connected between said power source and each of said first and second pulse circuits to reset said first and second pulse circuits to a prescribed condition when said power source has returned to a prescribed level.
Claim 2
Dependent Claim
134 words
A circuit for detecting the condition of a power source comprising, a first pulse circuit (1, OS1) for selectively generating pulses (D) of a first time period and frequency as a function of the signal (C) supplied thereto from said power source, a second pulse circuit (OS2) for selectively generating pulses (E) of a second time period and frequency as a function of the pulses (D) supplied thereto by said first pulse circuit, said second pulse circuit selectively supplying pulses to said first pulse circuit to effectively disable said first pulse circuit, and reset circuit means (2, etc) connected between said power source and each of said first and second pulse circuits to reset said first and second pulse circuits to a prescribed condition when said power source has returned to a prescribed level.
Claim 3
Dependent Claim
20 words
The circuit recited in claim 1 including pulse shaping means connected between said power source and said first pulse circuit.
Claim 4
Dependent Claim
16 words
The circuit recited in claim 2 wherein, said pulse shaping means comprises a first comparator circuit.
Claim 5
Dependent Claim
16 words
The circuit recited in claim 1, wherein, said reset circuit means comprises a second comparator circuit.
Claim 6
Dependent Claim
39 words
The circuit recited in claim 1 including, means connected between said power source and said first pulse circuit to vary the time period of said pulses generated thereby as a function of the signal supplied by said power source.
Claim 7
Dependent Claim
20 words
The circuit recited in claim 1 wherein, said first and second pulse circuits comprise first and second one-shot circuits, respectively.
Claim 8
Dependent Claim
13 words
The circuit recited in claim 6 wherein, said first one-shot circuit is retriggerable.
Claim 9
Dependent Claim
42 words
The circuit recited in claim 2 wherein, said pulse shaping means is connected to said power source and to a reference signal source to produce output signals only when said poer source provides a signal which is greater than said reference signal.
Claim 10
Dependent Claim
18 words
The circuit recited in claim 1 wherein, said power source is transformer coupled to said first pulse circuit.
Claim 11
Dependent Claim
20 words
The circuit recited in claim 9 including, full wave rectifier means connected between the transformer and said first pulse circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-18 | 1987-01-17 | 1987-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-18 | 1991-01-17 | 1991-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-18 | 1995-01-17 | 1995-07-19 | $7700.00 | Window Closed / Lapsed |