Loop switching system

Claim 2

A communication system for serially interconnecting n communication circuits (T1-Tm, ST(n-m)-Stn) comprising: n port means (103-1 to 103-n), each having an input (SDI-i) and an output terminal (SDO-i), associated on a one-to-one basis with said n communication circuits (T1-Tm, ST(n-m)-STn) for interfacing said n communication circuits (T1-Tn, ST(n-m)-STn) to said communication system; control means (101) for establishing an order of interconnection for all of said n port means; and interconnection means (100) connected to said input (SDI-i) and said output (SDO-i) terminals of all of said n port means (103-1 to 103-n) and responsive to said control means (101) for carrying data messages from said output terminal (SDO-(m+1)) of the (m+1)th port means (103-(m+1)) to said input terminal (SDI-m) of the m th port means (103-m) for all n said port means (103-1 to 103-n) according to said order of interconnection.

Claim 3

The invention of claim 1 wherein said communication system includes loop length adjusting means (102) connected to said interconnection means (100) for delaying the transmission of said data messages among said n port means (103-1 to 103-n) by a length of time sufficient to make the data message transit time through all said n port means (103-1 to 103-n) equal to a predetermined time.

Claim 4

The invention of claim 2 wherein said loop length adjusting means (102) has input (SDI-0) and output (SDO-0) terminals connected to said interconnection means (100); and wherein said interconnection means (100) carries each data message from the output terminal (SDO-1) of a selected first port means (103-1) to said input terminal (SDI-0) of said loop length adjusting means (102) wherein said data message is delayed before being outputted by said loop length adjusting means (102) on said output terminal (SDO-0); and wherein said interconnection means (100) carries each of said delayed data messages from said loop length adjusting means (102) output terminal (SDO-0) to the input terminal (SDI-n) of a second selected port means (103-n).

Claim 5

The invention of claim 3 wherein said loop length adjusting means (102) includes offset calculator means (510) responsive to said control means (101) and the receipt of said data message for dynamically generating an offset signal which is indicative of the length of time said data message must be delayed to make the data message transit time through all said n port means (103-1 to 103-n) equal to said predetermined time.

Claim 6

The invention of claim 4 wherein said loop length adjusting means (102) includes delay means (511) responsive to said offset signal for delaying the outputting of said data signal on said loop length adjusting means (102) output terminal (SDO-0) by said length of time represented by said offset signal.

Claim 7

A communication system for serially interconnecting n communication circuits (T1-Tm, ST(n-m)-STn) comprising: n port means (103-1 to 103n), each having an input (SDI-i) and an output terminal (SDO-i), associated on a one-to-one basis with said n communication circuits (T1-Tm, ST(n-m)-STn) for interfacing said n communication circuits (T1-Tm, ST(n-m)-STn) to said communication system; control means (101) for establishing an order of interconnection for all of said n port means (103-1 to 103-n); interconnection means (100) connected to said input (SDI-i) and said output (SDO-i) terminals of all of said n port means (103-1 to 103n) and responsive to said control means (101) for carrying data messages from said output terminal (SDO-(m+1)) of the (m+1) th port means (103(m+1)) to said input terminal SDI-(m) of the m th port means (103-m for all said n port means (103-1 to 103-n) according to said order of interconnection; clock means (604) connected to each of said n port means (103-1 to 103-n) for generating control and timing signals to define time slot intervals; and wherein each of said n port means (103-(m+1)) is responsive to said control and timing signals for transmitting a single bit of said data message to the subsequent one of said n port means (103-m) via said interconnection means (100) during each of said time slot intervals.

Claim 8

A communication system for serially interconnecting n communication circuits (T1-Tm, ST(n-m)-STn) comprising: n port means (103-1 to 103n), each having an input (SDI-i) and an output terminal (SDO-i), associated on a one-to-one basis with said n communication circuits (T1-Tm, ST(n-m)-STn) for interfacing said n communication circuits (T1-Tm, ST(n-m)-STn) to said communication system; control means (101) for establishing an order of interconnection for all of said n port means (103-1 to 103-n); interconnection means (100) connected to said input (SDI-i) and said output (SDO-i) terminals of all of said n port means (103-1 to 103n) and responsive to said control means (101) for carrying data messages from said output terminal (SDO-(m+1)) of the (m+1) th port means (103(m+1)) to said input terminal SDI-(m) of the m th port means (103-m for all said n port means (103-1 to 103-n) according to said order of interconnection; clock means (604) connected to each of said n port means (103-1 to 103-n) for generating control and timing signals to define time slot intervals; and wherein each of said n port means (103-(m+1)) is responsive to said control and timing signals for transmitting a single bit of said data message to the subsequent one of said n port means (103-m) via said interconnection means (100) during each of said time slot intervals.

Claim 9

The invention of claim 6 wherein said communication system includes loop length adjusting means (102) connected to said interconnection means (100) for delaying the transmission of said data messages among said n port means (103-1 to 103-n) by an integral number of said time slot intervals.

Claim 10

The invention of claim 7 wherein said integral number of time slot intervals is equal to k times the data message repetition rate less n+1 times said time slot interval wherein k is the integer which represents the least number of data messages required to exceed n+1 times said time slot interval.

Claim 11

The invention of claim 8 wherein said loop length adjusting means (102) are responsive to said control means (101) for dynamically determining said integral number of time slot intervals.

Claim 12

The invention of claim 9 wherein said loop length adjusting means (102) has input (SDI-0) and output (SDO-0) terminals connected to said interconnection means (100); and wherein said interconnection means (100) carries each data message from the output terminal (SDI-1) of a first port means (103-1) to said input terminal (SDI-0) of said loop length adjusting means (102) wherein said data message is delayed said integral number of time slot intervals before being outputted by said loop length adjusting means (102) on said output terminal (SDO-0); and wherein said interconnection means (100) carries each of said delayed data messages from said loop length adjusting means (102) output terminal (SDO-0) to the input terminal (SDI-n) of a second port means (103-n).

Claim 13

The invention of claim 10 wherein said loop length adjusting means (102) includes offset calculator means (510) responsive to said control means (101) and the receipt of said data message for dynamically generating an offset signal which is indicative of said integral number of time slot intervals.

Claim 14

The invention of claim 11 wherein said loop length adjusting means (102) includes delay means (511) responsive to said offset signal for delaying the outputting of said data signal on said loop length adjusting means (102) output terminal (SDO-0) by said integral number of time slot intervals represented by said offset signal.

Claim 15

The invention of claims 2 or 7 wherein each of said n port means (103-m) includes error checking means (200) connected to said control means (101) and responsive to the receipt of a data message containing a transmission error on said input terminal (SDI-m) of said port means (103-m) for transmitting an error signal to said control means (101).

Claim 16

The invention of claim 13 wherein said control means (101) is responsive to the receipt of a persistent error signal from one or more of said n port means (103-1 to 103-n) for identifying the disabled one of said n port means (103-m) that is the source of said transmission error and for removing said disabled port means (103-m) from said order of interconnection.

Claim 17

The invention of claims 1 or 6 wherein said interconnection means (100) comprises a PNPN electronic crosspoint matrix.