Abstract In modern digital telecommunications switching networks the switch block may be a duplicated plane time-space-time arrangement in which each time switch stage and each space switch stage is controlled by control stores. Each control store is cross-office slot ordered and is arranged to be loaded by the central control with the identity of the connection required for the relevant cross-office slot. At each busy cross-office slot in a time switch control store a 12 bit address word is retrieved. Ten bits are used to define the connection while the two remaining bits act as a busy bit and a parity bit. Each space switch control store contains in cross-office slot order eight bit address words (6 bits address plus busy and parity bits). The busy bits are used when interrogating the trunking for free paths and they are also used to control the application of idle codes to free slots in the speech path. The parity bits within the control stores are used to initiate pattern insertion on the speech highways. The detection of "bad parity" causes characteristic patterns to replace an erroneously accessed samples at the time or space switch and the replaced sample will be intercepted at the transmit digital line termination unit, which will be biased to choose the sample from the other plane of the switch block. The inserted pattern also identifies the trunking element to which the erroneous address has been applied so that the DLT is able to indicate the faulty control store.
Inventors
👤 Ernest Culley
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-26 15:12
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
125 words
A telecommunications exchange switching network including time and space switching stages in which each time and space switching stage includes connection control stores arranged to be cyclically read in cross-office slot order to provide the speech path connection information for each cross-office slot and each control store includes checking means arranged to check the authenticity of the connection specified by the control store at each cross-office slot and each switching stage includes fault pattern injection means arranged to be activated, in the event that said checking means detects an error, to inject a characteristic pattern, which is a corrupted speech sample and is indicative of the identity of the switching store, into the speech path defined by the connection control store in a particular slot.
Claim 2
Dependent Claim
125 words
A telecommunications exchange switching network including time and space switching stages in which each time and space switching stage includes connection control stores arranged to be cyclically read in cross-office slot order to provide the speech path connection information for each cross-office slot and each control store includes checking means arranged to check the authenticity of the connection specified by the control store at each cross-office slot and each switching stage includes fault pattern injection means arranged to be activated, in the event that said checking means detects an error, to inject a characteristic pattern, which is a corrupted speech sample and is indicative of the identity of the switching store, into the speech path defined by the connection control store in a particular slot.
Claim 3
Dependent Claim
39 words
A telecommunications exchange switching network according to claim 1 in which each switching stage is allocated a unique identity and each fault pattern injection means is programmed with the unique identity of the switching stage in which it resides.
Claim 4
Dependent Claim
75 words
A telecommunications exchange switching network according to claim 2 in which each control store location includes a parity bit indicative of the parity of the connection address stored at that location, and the checking means is arranged to compute the parity for each connection address read from the control store and to compare the computed parity with the stored parity and if they do not equate, the checking means activates the fault pattern injection means.