Circuit for reducing voltage stress across a transformer

Claim 1

A circuit for reducing voltage stress on a first transformer having a primary and a secondary, wherein a load coupled to said secondary has a first voltage thereacross, and an output terminal is connected to said load, to which a second voltage is applied that is much greater than said first voltage; said circuit comprising: at least one additional transformer, so that the total number of transformers is an integer n, each transformer having a primary and a secondary, wherein the primary of the jth transformer is connected to the secondary of the (j-1)st transformer for all j such that 2≦j≦n, and the secondary of the nth transformer is coupled to said load; and a voltage dividing network for shifting some of said second voltage from across said first transformer to across said additional transformer(s), said voltage dividing network comprising: n resistors, with one resistor connected between a primary and a secondary of each transformer; and n capacitors, each resistor having a capacitor connected thereacross; where RJ(Cj+CTj)=Rk(Ck+CTk) for all integers j, k such that 1≦j≦n and 1≦k≦n, where Rj is the resistance of the jth resistor, Cj is the capacitance of the jth capacitor, CTj is the interwinding capacitance of the jth transformer, Rk is the resistance of the kth resistor, Ck is the capacitance of the kth capacitor, and CTk is the interwinding capacitance of the kth transformer.