US4389723A
Expired / Lapsed
US
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High-speed pattern generator
Assignee: Ando Electric Co Ltd
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Filing: 1981-01-14
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Granted: 1983-06-21
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Expires: 2001-01-14
Abstract
Abstract A high-speed pattern generator includes a plurality of arithmetic and logic units (ALUs) which are n in number and have m-bit outputs, n registers receptive as inputs as outputs from the ALUs, and n-bit shift registers which are m in number, each ALU and connected register being unitized and coupled to the shift registers. The outputs of the registered input data are applied to the ALUs. The unitized ALUs and registers produce outputs applied in the same sequence to bits of the shift registers, which are responsive to clock pulses to generate a pattern output at a high speed.
Inventors
- 👤 Atsushi Nigorikawa
- 👤 Hiroshi Yokoyama
- 👤 Takanori Fujieda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
147 words
A high-speed pattern generator comprising a plurality of n (n≧2) of units, said units comprising a plurality of n arithmetic and logic units (hereinafter referred to as "ALUs") having outputs in m bits (m≧1) and a plurality of n registers having outputs and also having inputs for receiving the outputs from said ALUs, the outputs of one of (a) said plurality of ALUs and (b) said plurality of registers being the outputs of said units, said generator further comprising a plurality m of n-bit shift registers, said ALUs having inputs for receiving input data and receiving outputs from said registers, said shift registers having inputs connected for receiving the outputs of said units in a manner to supply the outputs of the ith (n≧i≧1) unit to ith bit inputs of said shift registers in the same sequence, thereby enabling said shift registers to produce a pattern output.
Claim 2
Dependent Claim
147 words
A high-speed pattern generator comprising a plurality of n (n≧2) of units, said units comprising a plurality of n arithmetic and logic units (hereinafter referred to as "ALUs") having outputs in m bits (m≧1) and a plurality of n registers having outputs and also having inputs for receiving the outputs from said ALUs, the outputs of one of (a) said plurality of ALUs and (b) said plurality of registers being the outputs of said units, said generator further comprising a plurality m of n-bit shift registers, said ALUs having inputs for receiving input data and receiving outputs from said registers, said shift registers having inputs connected for receiving the outputs of said units in a manner to supply the outputs of the ith (n≧i≧1) unit to ith bit inputs of said shift registers in the same sequence, thereby enabling said shift registers to produce a pattern output.
Claim 3
Dependent Claim
21 words
A high-speed pattern generator according to claim 1, wherein the outputs from said ALUs serve as said outputs of said units.
Claim 4
Dependent Claim
21 words
A high-speed pattern generator according to claim 1, wherein the outputs from said registers serve as said outputs of said units.
Claim 5
Dependent Claim
46 words
A high-speed pattern generator according to claim 2, wherein said n units further include a plurality of n of data selectors interposed between the outputs of the n ALUs and the inputs of the n registers, said n data selectors having inputs for receiving input data.
Claim 6
Dependent Claim
95 words
A high-speed pattern generator according to claim 1, further comprising, for applying said data to said data inputs of said ALUs, a control arrangement having a furher register with an output applied to the data inputs of said ALUs, a pattern memory the stored content of which is applied to said further register, a control unit and a memory control for controlling the address of the pattern memory under the command of the control unit, and an ALU control for controlling the mode of operation of the ALUs under the command of the control unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-20 | 1986-12-20 | 1987-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-20 | 1990-12-20 | 1991-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-20 | 1994-12-20 | 1995-06-21 | $7700.00 | Window Closed / Lapsed |