US4388719A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic signal generator
Assignee: LORANGER TESTING Corp
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Filing: 1981-01-16
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Granted: 1983-06-14
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Expires: 2001-01-16
Abstract
Abstract A dynamic signal generating circuit for exercising semiconductors and other electronic devices and circuits which includes first and second address selectors, first and second PROM address counters connected to said first and second address selectors respectively, first and second interval timer PROMs connected to said first and second address counters respectively, first and second output signal PROMs connected to said first and second interval PROMs respectively and means to connect said first output signal PROMs through clock and address drivers to a device under test and means to connect said second output signal PROMs through clock drivers to said device being tested and means connecting said first output PROMs through data drivers to said device being tested whereby said circuit controls a dynamic signal pattern system for exercising said semiconductors or other electronic devices and circuits.
Inventors
- 👤 George E. Soltysik
- 👤 John C. R. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/2832; G01R31/2836; G01R31/2839; G01R31/2841; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C17/00; G11C17/14
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
398 words
A dynamic signal generating circuit for semiconductors comprising: a first starting address selector 11 and a second starting address selector 22, a first address counter means 12 and second address counter means 23, first interval counter means 13 and second interval counter means 24, first interval time means 14 and second interval time means 25, first output signal means 15 and second output signal means 26, an address counter 16, a programming card 17, address multiplexers 18, address signal means 21, data pattern generators 19, and data signal means 20, clock drivers 57, address drivers 58, data driver means 59, said starting address selectors 11 and 22 being connected to said first address counter means 12 and said second address counter means 23 respectively, said first address counter means 12 being connected to said first interval timer means 14 and to said first output signal means 15 respectively, said first interval timer means 14 being connected through said first interval counter 13 to said first address counter means 12, said second address counter means 23 being connected through said second interval timer means 25 to second interval counter means 24, said second address counter means 23 being also connected to said second output signal means 26, said second interval timer means 25 being connected through said second interval counter 24 to said second address counter 23, said first output signal means 15 being connected through said address counter means 16 to said programming card 17, said programming card 17 being connected to said data pattern generators 19, to said address multiplexers 18, and to said address signal means 21, said address multiplexers 18 being connected to said address signal means 21, said data pattern generator 19 being connected to said data signal means 20 and then connected through said data drivers means 59 to devices under test, said address signal means 21 being connected through address drivers 58 to said device under test, said first output signal means 15 and said second output signal means 26 being adapted to be connected through said clock drivers 57 to said device under test whereby a wide range of frequency and amplitude and intervals of signals is adjusted in said circuit and it is adapted to provide at least ten signals of all extremes at one time and to change from said ten signals to any one of different characters instantaneously.
Claim 2
Dependent Claim
398 words
A dynamic signal generating circuit for semiconductors comprising: a first starting address selector 11 and a second starting address selector 22, a first address counter means 12 and second address counter means 23, first interval counter means 13 and second interval counter means 24, first interval time means 14 and second interval time means 25, first output signal means 15 and second output signal means 26, an address counter 16, a programming card 17, address multiplexers 18, address signal means 21, data pattern generators 19, and data signal means 20, clock drivers 57, address drivers 58, data driver means 59, said starting address selectors 11 and 22 being connected to said first address counter means 12 and said second address counter means 23 respectively, said first address counter means 12 being connected to said first interval timer means 14 and to said first output signal means 15 respectively, said first interval timer means 14 being connected through said first interval counter 13 to said first address counter means 12, said second address counter means 23 being connected through said second interval timer means 25 to second interval counter means 24, said second address counter means 23 being also connected to said second output signal means 26, said second interval timer means 25 being connected through said second interval counter 24 to said second address counter 23, said first output signal means 15 being connected through said address counter means 16 to said programming card 17, said programming card 17 being connected to said data pattern generators 19, to said address multiplexers 18, and to said address signal means 21, said address multiplexers 18 being connected to said address signal means 21, said data pattern generator 19 being connected to said data signal means 20 and then connected through said data drivers means 59 to devices under test, said address signal means 21 being connected through address drivers 58 to said device under test, said first output signal means 15 and said second output signal means 26 being adapted to be connected through said clock drivers 57 to said device under test whereby a wide range of frequency and amplitude and intervals of signals is adjusted in said circuit and it is adapted to provide at least ten signals of all extremes at one time and to change from said ten signals to any one of different characters instantaneously.
Claim 3
Dependent Claim
283 words
A dynamic signal generating circuit for semiconductors comprising a first starting address selector means 11 and a second starting address selector 22, first address counter means 12 and second address counter means 23, first interval timer means 14, first interval counter means 13, second interval timer means 25, second interval counter means 24, and first output signal means 15, and second output signal means 26, an address counter 16, a programming card 17, address multiplexers 18, address signal means 21, data pattern generators 19, and data signal means 20, clock drivers 57, said starting address selector means 11 and 22 being connected to said first and second address counters means 12 and 23 respectively, said first interval timer means 14 being connected to said first address counter means 12, said first interval counter 13 being connected to said first interval timer 14 and to said first address counter means 12, said first output signal means 15 being connected through said first address counter means 12 and said first interval timer means 14, said second interval timer means 25 being connected to said second address counter means 23, said second interval counter 24 being connected to said second interval timer means 25 and to said second address counter means 23, said second output signal means 26 being connected to said second address counter means 23 and second interval timer means 25, first connecting means 42-45 and 53-56 adapted to connect said output signal means 15 and 26 directly to said clock drivers 57 and second connecting means 16-21 adapted to connect said first output signal means 15 to address drivers, whereby said circuit controls a dynamic signal pattern in a device to be tested.
Claim 4
Dependent Claim
283 words
A dynamic signal generating circuit for semiconductors comprising a first starting address selector means 11 and a second starting address selector 22, first address counter means 12 and second address counter means 23, first interval timer means 14, first interval counter means 13, second interval timer means 25, second interval counter means 24, and first output signal means 15, and second output signal means 26, an address counter 16, a programming card 17, address multiplexers 18, address signal means 21, data pattern generators 19, and data signal means 20, clock drivers 57, said starting address selector means 11 and 22 being connected to said first and second address counters means 12 and 23 respectively, said first interval timer means 14 being connected to said first address counter means 12, said first interval counter 13 being connected to said first interval timer 14 and to said first address counter means 12, said first output signal means 15 being connected through said first address counter means 12 and said first interval timer means 14, said second interval timer means 25 being connected to said second address counter means 23, said second interval counter 24 being connected to said second interval timer means 25 and to said second address counter means 23, said second output signal means 26 being connected to said second address counter means 23 and second interval timer means 25, first connecting means 42-45 and 53-56 adapted to connect said output signal means 15 and 26 directly to said clock drivers 57 and second connecting means 16-21 adapted to connect said first output signal means 15 to address drivers, whereby said circuit controls a dynamic signal pattern in a device to be tested.
Claim 5
Dependent Claim
16 words
The combination recited in claim 2 wherein said second connecting means comprises an address counter (16).
Claim 6
Dependent Claim
19 words
The dynamic signal generating circuit recited in claim 2 wherein said first connecting means 42-45 comprises a direct connection.
Claim 7
Dependent Claim
18 words
The circuit recited in claims 2, or 4 wherein said second connecting means comprises a programming card (17).
Claim 8
Dependent Claim
21 words
The circuit recited in claim 5 wherein said second connecting means comprises data pattern generators 19 connected to said programming card.
Claim 9
Dependent Claim
174 words
A dynamic signal generating circuit for semiconductors comprising, a first and second address selector (11,22), first and second address counters (12,23), first and second interval counters (13,24), first and second interval timer proms (14,25), first and second output signal proms (15,26), said first and second address selectors (11,22) being connected to said first and second address counters (12,23) respectively, said first and second interval counters (13,24) being connected to said first and second address counters (12,23) respectively, said first and second address counters (12,23) being connected to said first and second interval timer proms (14,25) respectively and to said first and second output signal proms (15,26) respectively, clock drivers (57), said first and second output signal proms (15,26) being connected to said clock drivers (57), and first circuit means (16, 17, 18, 21) connecting said first output signal proms to address drivers (57), and second circuit means (19,20) connecting said first circuit means to data drivers and means connecting said clock drivers, said address drivers, and said data drivers to a device under test.
Claim 10
Dependent Claim
174 words
A dynamic signal generating circuit for semiconductors comprising, a first and second address selector (11,22), first and second address counters (12,23), first and second interval counters (13,24), first and second interval timer proms (14,25), first and second output signal proms (15,26), said first and second address selectors (11,22) being connected to said first and second address counters (12,23) respectively, said first and second interval counters (13,24) being connected to said first and second address counters (12,23) respectively, said first and second address counters (12,23) being connected to said first and second interval timer proms (14,25) respectively and to said first and second output signal proms (15,26) respectively, clock drivers (57), said first and second output signal proms (15,26) being connected to said clock drivers (57), and first circuit means (16, 17, 18, 21) connecting said first output signal proms to address drivers (57), and second circuit means (19,20) connecting said first circuit means to data drivers and means connecting said clock drivers, said address drivers, and said data drivers to a device under test.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-13 | 1986-12-13 | 1987-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-13 | 1990-12-13 | 1991-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-13 | 1994-12-13 | 1995-06-14 | $7700.00 | Window Closed / Lapsed |