Abstract In a transducer signal processing system wherein the output signal generated by a transducer (14) includes a nearly d.c., relatively large amplitude drift component (12), a higher frequency end point, data component (10) and a high frequency noise (hash) component (11), the drift and hash components are substantially eliminated by supplying the composite transducer output signal to a pair of parallel integrator circuits (28, 30) having different integration time constants. The faster integrator (28) passes the drift and data signal components, while attenuating the hash component, whereas the slower integrator (30) passes the drift component and attenuates the data and hash components. The output of the slower integrator (30) is subtracted from the output of the faster integrator (28) to provide a resultant signal containing essentially only the transducer data component.
A circuit for reducing the d.c. outputted drift signal component from a transducer generated signal wherein the transducer signal includes the d.c. drift component to be reduced, a data component, and a high frequency noise component, said circuit comprising: first and second parallel integrator circuit means which receive and are responsive to said transducer signal; said first integrator circuit means having a first time constant set to pass the d.c. drift and data components of the received transducer signal while attenuating its received noise component; said second integrator circuit means having a second time constant set to be longer than the first time constant, said second integrator circuit means passes the said received d.c. drift and a smaller portion of the data component than that passed by the first integrator circuit means, said two integrator circuit means generating, respectively, first and second output signals; and circuit means for receiving said first and second output signals from the integrators and for subtracting said second output signal from said first output signal, the output signal from said subtracting means being a data component signal whose drift and noise component are continuously and automatically suppressed therein.
Claim 2
Dependent Claim
193 words
A circuit for reducing the d.c. outputted drift signal component from a transducer generated signal wherein the transducer signal includes the d.c. drift component to be reduced, a data component, and a high frequency noise component, said circuit comprising: first and second parallel integrator circuit means which receive and are responsive to said transducer signal; said first integrator circuit means having a first time constant set to pass the d.c. drift and data components of the received transducer signal while attenuating its received noise component; said second integrator circuit means having a second time constant set to be longer than the first time constant, said second integrator circuit means passes the said received d.c. drift and a smaller portion of the data component than that passed by the first integrator circuit means, said two integrator circuit means generating, respectively, first and second output signals; and circuit means for receiving said first and second output signals from the integrators and for subtracting said second output signal from said first output signal, the output signal from said subtracting means being a data component signal whose drift and noise component are continuously and automatically suppressed therein.
Claim 3
Dependent Claim
19 words
The circuit of claim 1, including display means coupled to said subtracting means for displaying said output signal therefrom.
Claim 4
Dependent Claim
26 words
The circuit of claim 2, including attenuator means coupled to said subtracting means for ranging said drift suppressed output signal for display on said display means.