Phase dependent SEM IC chip testing with voltage contrast

Claim 1

A method of examining timing delays in a dynamically operating integrated circuit (IC) utilizing a scanning electron microscope (SEM) comprising: dynamically operating the IC between two operating states with a clock means providing a first logic level and a second logic level, continuously scanning the IC with the SEM, continuously collecting the electrons emitted from the surface of the IC by a detector means in the SEM, presenting the output of the detector to one input of a first gate and to one input of a second gate, enabling the first gate by one logic level from the output of the clock means, enabling the second gate by the same logic level from an inverted output of the clock means, presenting the output of the first gate to one input of a differential amplifier means and the output of the second gate to the second input of the differential amplifier means, presenting the output of the differential amplifier to the SEM display means wherein the timing delay of a change in logic level of an observed area of the IC from a change in logic level of the clock means is determined by examination of the brightness of the observed area relative to unoperated areas of the IC such that maximum brightness contrast occurs at 2nT/4 and minimum contrast occurs at (2n+1)T/4, where T is the clock period and n is an integer.

Claim 2

A method of examining timing delays in a dynamically operating integrated circuit (IC) utilizing a scanning electron microscope (SEM) comprising: dynamically operating the IC between two operating states with a clock means providing a first logic level and a second logic level, continuously scanning the IC with the SEM, continuously collecting the electrons emitted from the surface of the IC by a detector means in the SEM, presenting the output of the detector to one input of a first gate and to one input of a second gate, enabling the first gate by one logic level from the output of the clock means, enabling the second gate by the same logic level from an inverted output of the clock means, presenting the output of the first gate to one input of a differential amplifier means and the output of the second gate to the second input of the differential amplifier means, presenting the output of the differential amplifier to the SEM display means wherein the timing delay of a change in logic level of an observed area of the IC from a change in logic level of the clock means is determined by examination of the brightness of the observed area relative to unoperated areas of the IC such that maximum brightness contrast occurs at 2nT/4 and minimum contrast occurs at (2n+1)T/4, where T is the clock period and n is an integer.

Claim 3

A method of examining a property of a dynamically operating integrated circuit (IC) having at least two operating states utilizing a scanning electron microscope (SEM) comprising: dynamically operating the IC under the control of a logic sequencer means, continuously scanning the IC with the SEM, continuously collecting the electrons emitted from the surface of the IC by a detector means in the SEM, presenting the output of the detector to one input of a first gate and to one input of a second gate, enabling the first gate by the logic sequencer means for a period of time, enabling the second gate by the logic sequencer means for the period of time such that the second gate is not enabled before the termination of the enablement of the first gate, presenting the output of the first gate to one input of a differential amplifier means and the output of the second gate to the second input of the differential amplifier means, and presenting the output of the differential amplifier to the SEM display means, wherein the property examined is the logical level of an observed area of the IC wherein the enablement of the first gate is terminated not later than a change in logic level of an area of the IC under test and the enablement of the second gate is initiated not earlier than such change, such that the area under test will display a heightened contrast on the SEM monitor relative to non-operated areas of the IC.

Claim 4

A method of examining a property of a dynamically operating integrated circuit (IC) having at least two operating states utilizing a scanning electron microscope (SEM) comprising: dynamically operating the IC under the control of a logic sequencer means, continuously scanning the IC with the SEM, continuously collecting the electrons emitted from the surface of the IC by a detector means in the SEM, presenting the output of the detector to one input of a first gate and to one input of a second gate, enabling the first gate by the logic sequencer means for a period of time, enabling the second gate by the logic sequencer means for the period of time such that the second gate is not enabled before the termination of the enablement of the first gate, presenting the output of the first gate to one input of a differential amplifier means and the output of the second gate to the second input of the differential amplifier means, and presenting the output of the differential amplifier to the SEM display means, wherein the property examined is the logical level of an observed area of the IC wherein the enablement of the first gate is terminated not later than a change in logic level of an area of the IC under test and the enablement of the second gate is initiated not earlier than such change, such that the area under test will display a heightened contrast on the SEM monitor relative to non-operated areas of the IC.

Claim 5

A method of examining a property of a dynamically operating integrated circuit (IC) having at least two operating states utilizing a scanning electron microscope (SEM) comprising: dynamically operating the IC under the control of a logic sequencer means, continuously scanning the IC with the SEM, continuously collecting the electrons emitted from the surface of the IC by a detector means in the SEM, presenting the output of the detector to one input of a first gate and to one input of a second gate, enabling the first gate by the logic sequencer means for a period of time, enabling the second gate by the logic sequencer means for the period of time such that the second gate is not enabled before the termination of the enablement of the first gate, presenting the output of the first gate to one input of a differential amplifier means and the output of the second gate to the second input of the differential amplifier means, and presenting the output of the differential amplifier to the SEM display means, wherein the property examined is the timing delay between a change in state of a first logic function in the dynamically operating IC and a change in state in a second logic function of the IC wherein the enablement of the first gate is terminated essentially simultaneously with a change in logic level in the first logic function area of the IC and the initialization of the enablement of the second gate is measurably adjusted to essentially coincide with the same relative change in logic level in the second logic function area of the IC, such that the proper adjustment is marked by an increase in contrast on the SEM monitor of the second area relative to non-operated areas of the IC.

Claim 6

A method of examining a property of a dynamically operating integrated circuit (IC) having at least two operating states utilizing a scanning electron microscope (SEM) comprising: dynamically operating the IC under the control of a logic sequencer means, continuously scanning the IC with the SEM, continuously collecting the electrons emitted from the surface of the IC by a detector means in the SEM, presenting the output of the detector to one input of a first gate and to one input of a second gate, enabling the first gate by the logic sequencer means for a period of time, enabling the second gate by the logic sequencer means for the period of time such that the second gate is not enabled before the termination of the enablement of the first gate, presenting the output of the first gate to one input of a differential amplifier means and the output of the second gate to the second input of the differential amplifier means, and presenting the output of the differential amplifier to the SEM display means, wherein the property examined is the timing delay between a change in state of a first logic function in the dynamically operating IC and a change in state in a second logic function of the IC wherein the enablement of the first gate is terminated essentially simultaneously with a change in logic level in the first logic function area of the IC and the initialization of the enablement of the second gate is measurably adjusted to essentially coincide with the same relative change in logic level in the second logic function area of the IC, such that the proper adjustment is marked by an increase in contrast on the SEM monitor of the second area relative to non-operated areas of the IC.