US4385328A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data extracting circuit
Assignee: Sony Corp
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Filing: 1980-10-16
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Granted: 1983-05-24
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Expires: 2000-10-16
Abstract
Abstract A data extracting circuit including an input terminal supplied with an input signal which is reproduced from a magnetic tape, positive and negative peak hold circuits connected to the input terminal, respectively, an adding circuit for adding the positive and negative peak voltages from the peak hold circuits at a predetermined rate and for producing a threshold voltage, and a level comparator having a first input terminal supplied with the delayed input signal and a second input terminal supplied with the threshold voltage and for deriving a digital binary data signal, the positive and negative peak hold circuits including a higher level priority circuit and a lower level priority circuit, respectively, and supplied with the input signal and a delayed signal which is further delayed by a second delay circuit following the delay circuit.
Inventors
- 👤 Masato Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:08
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/061; H04L25/062; G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
139 words
A data extracting circuit comprising: (a) an input terminal supplied with an input signal; (b) a level comparator having first and second input terminals and an output terminal; (c) a delay circuit connected between said input terminal and said first input terminal of said level comparator and having delay time shorter than the minimum transition period of said input signal; (d) a positive peak hold circuit and a negative peak hold circuit connected to said input terminal and having relatively small time constants respectively; and (e) an adding circuit connected between said positive and negative peak hold circuits and the second input terminal of said level comparator for adding the outputs of said positive and negative peak hold circuits at a predetermined rate which is supplied to the second input terminal of said level comparator as a threshold level.
Claim 2
Dependent Claim
139 words
A data extracting circuit comprising: (a) an input terminal supplied with an input signal; (b) a level comparator having first and second input terminals and an output terminal; (c) a delay circuit connected between said input terminal and said first input terminal of said level comparator and having delay time shorter than the minimum transition period of said input signal; (d) a positive peak hold circuit and a negative peak hold circuit connected to said input terminal and having relatively small time constants respectively; and (e) an adding circuit connected between said positive and negative peak hold circuits and the second input terminal of said level comparator for adding the outputs of said positive and negative peak hold circuits at a predetermined rate which is supplied to the second input terminal of said level comparator as a threshold level.
Claim 3
Dependent Claim
90 words
A data extracting circuit according to claim 1, wherein said positive peak hold circuit includes a higher level priority circuit supplied with said input signal and the output of said delay circuit and outputs a higher peak voltage in said input signal and the output of said delay circuit, and said negative peak hold circuit includes a lower level priority circuit supplied with said input signal and the output of said delay circuit and outputs a lower peak voltage in said input signal and the output of said delay circuit.
Claim 4
Dependent Claim
30 words
A data extracting circuit according to claim 1 further comprising a second delay circuit connected between the output of said delay circuit and said positive and negative peak hold circuits.
Claim 5
Dependent Claim
33 words
A data extracting circuit according to claim 3, wherein the delay time of said second delay circuit is selected shorter than the delay time of said delay circuit connected with said input terminal.
Claim 6
Dependent Claim
164 words
A data extracting circuit comprising an input terminal receiving an input data signal, a delay means connected to said input terminal with a delay of one-half the rise and fall time of said input signal, a buffer amplifier receiving the output of said delay means, a level comparator receiving a first input from said buffer amplifier, a positive peak hold circuit with a pair of input positively poled diodes and one of said diodes connected to said input terminal and the other diodes connected to the output of said buffer amplifier, a negative peak hold circuit with a pair of input negatively poled diodes and one of said diodes connected to said input terminal and the other diode connected to the output of said buffer amplifier, and an adding circuit connected to the outputs of said positive and negative peak hold circuits and supplying a second input to said level comparator and said positive and negative peak hold circuits have relatively small time constants.
Claim 7
Dependent Claim
164 words
A data extracting circuit comprising an input terminal receiving an input data signal, a delay means connected to said input terminal with a delay of one-half the rise and fall time of said input signal, a buffer amplifier receiving the output of said delay means, a level comparator receiving a first input from said buffer amplifier, a positive peak hold circuit with a pair of input positively poled diodes and one of said diodes connected to said input terminal and the other diodes connected to the output of said buffer amplifier, a negative peak hold circuit with a pair of input negatively poled diodes and one of said diodes connected to said input terminal and the other diode connected to the output of said buffer amplifier, and an adding circuit connected to the outputs of said positive and negative peak hold circuits and supplying a second input to said level comparator and said positive and negative peak hold circuits have relatively small time constants.
Claim 8
Dependent Claim
200 words
A data extracting circuit comprising an input terminal receiving an input data signal, a first delay means connected to said input terminal with a delay a little larger than one-half the rise and fall time of said input signal, a second delay means receiving an output of said first delay means and having a delay a little smaller than one-half the rise or fall times of the input signal, a level comparator receiving a first input from said first delay means, a buffer amplifier receiving an input from said second delay means, a positive peak hold circuit with a pair of input positively poled diodes and one of said diodes connected to said input terminal and the other diodes connected to the output of said buffer amplifier, a negative peak hold circuit with a pair of input negatively poled diodes and one of said diodes connected to said input terminal and the other diode connected to the output of said buffer amplifier, and an adding circuit connected to the outputs of said positive and negative peak hold circuits and supplying a second input to said level comparator and said positive and negative peak hold circuits have relatively small time constants.
Claim 9
Dependent Claim
200 words
A data extracting circuit comprising an input terminal receiving an input data signal, a first delay means connected to said input terminal with a delay a little larger than one-half the rise and fall time of said input signal, a second delay means receiving an output of said first delay means and having a delay a little smaller than one-half the rise or fall times of the input signal, a level comparator receiving a first input from said first delay means, a buffer amplifier receiving an input from said second delay means, a positive peak hold circuit with a pair of input positively poled diodes and one of said diodes connected to said input terminal and the other diodes connected to the output of said buffer amplifier, a negative peak hold circuit with a pair of input negatively poled diodes and one of said diodes connected to said input terminal and the other diode connected to the output of said buffer amplifier, and an adding circuit connected to the outputs of said positive and negative peak hold circuits and supplying a second input to said level comparator and said positive and negative peak hold circuits have relatively small time constants.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-23 | 1986-11-22 | 1987-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-23 | 1990-11-22 | 1991-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-23 | 1994-11-22 | 1995-05-24 | $7700.00 | Window Closed / Lapsed |