Semiconductor memory device

Claim 2

A semiconductor memory device comprising: a plurality of memory blocks each including: a row line; and a sense amplifier array comprising digit lines, and a plurality of sense amplifiers, operatively connected to said digit lines, each having a pair of input/output terminals; and a pair of memory cell groups each comprising a plurality of dynamic type memory cells which are selectively connected to said sense amplifier array through said digit lines; a row decoder, operativelyy connected to each row line of said plurality of memory blocks, for selecting one of the row lines in said plurality of memory blocks; pairs of bus lines, each pair corresponding to one of said sense amplifier arrays and each pair operatively connectable to corresponding pairs of said input/output terminals; column lines operatively connected to said pairs of bus lines; and a column decoder, operatively connected to said column lines, which is common to said plurality of memory blocks and which selectively connects one pair of input/output terminals of said sense amplifiers in each of said memory blocks to a corresponding one of said pairs of bus lines by changing the potential of one of said column lines connected between said column decoder and said plurality of memory blocks.

Claim 3

A semiconductor memory device as set forth in claim 1, wherein said column decoder is disposed along an outside edge of the area of said memory blocks.

Claim 4

A semiconductor memory device as set forth in claim 1, wherein said column decoder is disposed between said memory blocks.

Claim 5

A semiconductor memory device as set forth in claim 3, wherein said column decoder is disposed at the center of said memory blocks.

Claim 6

A semiconductor memory device as set forth in claim 1, wherein said column lines from said column decoder pass through the area of said memory blocks.

Claim 7

A semiconductor memory device as set forth in claim 5, further comprising gate transistors operatively connected between said pair of input/output terminals and a corresponding one of said pairs of bus lines, wherein said column lines are operatively connected to said gate transistors which selectively connect said pair of input/output terminals of the sense amplifier in each of said memory blocks to a corresponding one of said pairs of bus lines.

Claim 8

A semiconductor memory device as set forth in claim 1, wherein each of said pairs of bus lines is disposed parallel to said sense amplifier array of a corresponding one of said memory blocks.

Claim 9

A semiconductor memory device as set forth in claim 1, 2, 3, 4, 5, 6 or 7, wherein each of said dynamic type memory cells comprises a capacitor and an MOS transistor.

Claim 10

A semiconductor memory device comprising: a plurality of memory blocks each including: a row line; a sense amplifier array comprising a plurality of sense amplifiers and digit lines operatively connected to said sense amplifiers; and a pair of memory cell groups each comprising a plurality of dynamic type memory cells which are operatively connected to said sense amplifier aray through said digit lines and each of said memory cells comprising a capacitor operatively connected to ground and a MOS transistor operatively connected to said capacitor, one of said digit lines and one of said row lines, one of the electrodes of said capacitor being formed as a first conductive layer, and the gate electrode of said MOS transistor being formed as a second conductive layer; a row decoder, operatively connected to each row line of said plurality of memory blocks, for selecting one of said row lines in said plurality of memory blocks; pairs of bus lines, each pair corresponding to one of said sense amplifier arrays and each pair operatively connectable to a corresponding one of said sense amplifiers arrays; column lines operatively connected to said plurality of memory blocks and said pairs of bus lines; a column decoder, operatively connected to said column lines, which is common to said plurality of memory blocks and which selectively connects one pair of input/output terminals of said sense amplifiers in each of said memory blocks to a corresponding one of said pairs of bus lines by changing the potential of one of said column lines connected between said column decoder and said plurality of memory blocks, said digit lines being formed as a third conductive layer having a first electrical conductivity disposed on said first conductive layer and an insulation layer formed therebetween, said column lines also being formed as said third conductive layer having a first electrical conductivity, and said row lines being formed as a fourth layer having a second electrical conductivity disposed on said third conductive layer and having another insulation layer formed therebetween.

Claim 11

A semiconductor memory device comprising: a plurality of memory blocks each including: a row line; a sense amplifier array comprising a plurality of sense amplifiers and digit lines operatively connected to said sense amplifiers; and a pair of memory cell groups each comprising a plurality of dynamic type memory cells which are operatively connected to said sense amplifier aray through said digit lines and each of said memory cells comprising a capacitor operatively connected to ground and a MOS transistor operatively connected to said capacitor, one of said digit lines and one of said row lines, one of the electrodes of said capacitor being formed as a first conductive layer, and the gate electrode of said MOS transistor being formed as a second conductive layer; a row decoder, operatively connected to each row line of said plurality of memory blocks, for selecting one of said row lines in said plurality of memory blocks; pairs of bus lines, each pair corresponding to one of said sense amplifier arrays and each pair operatively connectable to a corresponding one of said sense amplifiers arrays; column lines operatively connected to said plurality of memory blocks and said pairs of bus lines; a column decoder, operatively connected to said column lines, which is common to said plurality of memory blocks and which selectively connects one pair of input/output terminals of said sense amplifiers in each of said memory blocks to a corresponding one of said pairs of bus lines by changing the potential of one of said column lines connected between said column decoder and said plurality of memory blocks, said digit lines being formed as a third conductive layer having a first electrical conductivity disposed on said first conductive layer and an insulation layer formed therebetween, said column lines also being formed as said third conductive layer having a first electrical conductivity, and said row lines being formed as a fourth layer having a second electrical conductivity disposed on said third conductive layer and having another insulation layer formed therebetween.

Claim 12

A semiconductor memory device as set forth in claim 9, wherein said column decoder is disposed along an outside edge of the area of said memory blocks.

Claim 13

A semiconductor memory device as set forth in claim 9, wherein said column decoder is disposed between said memory blocks.

Claim 14

A semiconductor memory device as set forth in claim 11, wherein said column decoder is disposed at the center of said memory blocks.

Claim 15

A semiconductor memory device as set forth in claim 9, wherein said column lines from said column decoder pass through the area of said memory blocks.

Claim 16

A semiconductor memory device as set forth in claim 9, wherein said first conductive layer is formed continuously on a semiconductor substrate and comprises a common electrode of said capacitors of all memory cells of said plurality of memory blocks.

Claim 17

A semiconductor memory device as set forth in claim 9, 10, 11, 12, 13 or 14, wherein each first conductive layer is made of polycrystalline silicone.

Claim 18

A semiconductor memory device as set forth in claim 9, 10, 11, 12, 13, or 14 wherein said second conductive layer is made of polycrystalline silicone.

Claim 19

A semiconductor memory device as set forth in claim 9, 10, 11, 12, 13 or 14, wherein said third conductive layer comprises metal having a high melting point.

Claim 20

A semiconductor memory device as set forth in claim 9, 10, 11, 12, 13 or 14, wherein said third conductive layer comprises a silicate with metal having a high melting point.

Claim 21

A semiconductor memory device as set forth in claim 9, 10, 11, 12, 13 or 14, wherein said third conductive layer comprises polycrystalline silicone.

Claim 22

A semiconductor memory device as set forth in claim 9, 10, 11, 12, 13 or 14, wherein said third conductive layer comprises aluminum.