Variable peaking control circuit

Claim 2

A circuit combination for processing a composite video signal, comprising: a video signal peaking circuit responsive to said composite video signal and having a peaking control signal input terminal for applying a peaking control signal to control the degree of peaking; first circuit means responsive to the unpeaked composite video signal for detecting impulse noise above a threshold level in blanking intervals of said composite video signal and for generating a further control signal having a duration of at least a video field period whenever said impulse noise is detected; a first source of peaking control signal; a second source of peaking control signal; and second circuit means responsive to said further control signal for selectively coupling said first source of peaking control signal to said control input terminal for a duration of at least one video field period and responsive to the absence of said further control signal for coupling said second source of peaking signal to said control input terminal.

Claim 3

Video signal processing circuitry comprising: defect substitution circuitry for replacing defective video signal segments with video signal segments advanced or delayed in time therefrom; defect detection circuitry responsive to defects in said video signal for generating a switching signal to control said defect substitution circuitry; a video signal peaking circuit having an input terminal connected to an output terminal of said substitution circuitry, and having a peaking control input terminal, said peaking circuit being responsive to a peaking control signal for establishing the degree of peaking applied to the video signal; first circuit means responsive to said switching signal and to video signal blanking signals for generating a further control signal when signal defects are detected during a blanking interval of said video signal, and wherein said further control signal is of at least one video field duration; a first and second source of peaking control signal; and second circuit means responsive to said further control signal for coupling said first source of peaking control signal to said peaking control input terminal for at least one video field period, and for coupling said second source of peaking control signal to said peaking control input terminal in the absence of said further control signal.

Claim 4

Video signal processing circuitry comprising: defect substitution circuitry for replacing defective video signal segments with video signal segments advanced or delayed in time therefrom; defect detection circuitry responsive to defects in said video signal for generating a switching signal to control said defect substitution circuitry; a video signal peaking circuit having an input terminal connected to an output terminal of said substitution circuitry, and having a peaking control input terminal, said peaking circuit being responsive to a peaking control signal for establishing the degree of peaking applied to the video signal; first circuit means responsive to said switching signal and to video signal blanking signals for generating a further control signal when signal defects are detected during a blanking interval of said video signal, and wherein said further control signal is of at least one video field duration; a first and second source of peaking control signal; and second circuit means responsive to said further control signal for coupling said first source of peaking control signal to said peaking control input terminal for at least one video field period, and for coupling said second source of peaking control signal to said peaking control input terminal in the absence of said further control signal.

Claim 5

The video signal processing circuitry set forth in claim 2 wherein the peaking circuit comprises: a signal delay element having an input terminal connected to said signal substitution circuit and having an output terminal; an signal subtracting circuit having first and second input terminals respectively connected to the signal delay element input and output terminals, and having an output terminal; a gain controlled amplifier having a signal input terminal connected to said signal subtracting circuit output terminal, a gain control signal terminal for applying said peaking control signals thereto, and having an output terminal; and a signal adding circuit having first and second input terminals respectively connected to said delay element and said amplifier output terminals, and having an output terminal at which peaked video signal is available.

Claim 6

The video signal processing circuitry set forth in claim 1 or 2 wherein said second circuit means and the first and second sources of peaking control signal comprise: a source of supply potential, and a reference potential; a first resistor having a first end connected to said supply potential, and having a second end; first and second resistive means having respective first terminals connected to the second end of said first resistor, and having respective second ends; first and second switch means, said first switch means connecting the second end of said first resistive means to reference potential only when the further control signal is present and said second switch means connecting the second end of said second resistive means to reference potential only when said further control signal is not present; and means for connecting the interconnection of the first resistor and the first and second resistive means to the control signal input terminal of said peaking circuit.

Claim 7

The video signal processing circuit set forth in claim 4 wherein the means connecting the interconnection of the first resistor and the first and second resistive means to said peaking circuit comprises; a buffer amplifier having an input terminal connected to said interconnection and having an ouput terminal, said amplifier having a low output impedance; a second resistor having first and second ends connected respectively to buffer amplifier output terminal and the peaking circuit control signal input terminal; and a capacitor connected between the second end of the second resistor and a point of fixed potential, said second resistor and said capacitor limiting the rate of potential transitions occurring at said peaking circuit control signal input terminal due to potential transitions produced at said buffer amplifier output terminal.

Claim 8

The video signal processing circuitry set forth in claim 4 wherein the first and second switch means comprise: an inverting amplifier having an input terminal connected for receiving said enabling signal and having an output terminal; first and second transistors having respective first and respective second electrodes with respective principal conduction paths therebetween, and having respective control electrodes, the first electrodes of said first and second transistors respectively connected to the second ends of the first and second resistive means, the second electrodes of said first and second transistors respectively connected to reference potential, and having their respective control electrodes connected to the input and output terminals of said inverting amplifier.

Claim 9

The video signal processing circuit set forth in claim 3 wherein the first circuit means comprises; a two input logic AND gate having a first input responsive to composite video signal blanking pulses and having a second input responsive to said signal defect detection circuitry, and having an output terminal; and a monostable multivibrator responsive to potential transitions occurring at the output terminal of said logic AND circuit for generating said further control signals of predetermined amplitude and duration.