US4381010A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Heart pacemaker with integrated injection logic energy saving circuitry
Assignee: Medtronic Inc
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Filing: 1981-04-03
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Granted: 1983-04-26
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Expires: 2001-04-03
Abstract
Abstract An implantable heart pacemaker having digital injection integrated circuitry includes a bias switch (70) operative to turn on or increase the bias current to the pulse width logic (50) just prior to an output pulse. Increased bias to the pulse width logic permits high speed operation of the logic to accurately terminate the output pulse at the end of the desired pulse duration. At the end of the output pulse, the bias switch is turned off to return the bias current to a low quiescent value, and in some cases is turned completely off, to conserve battery power. The logic gates used in the pulse width logic are arrayed along one or more current injector "bars" or "rails" formed in the integrated circuit, and the bias switch (70) is connected for controlling the current delivered to those current injectors, so that increased bias need only be supplied to the circuits requiring high switching speed.
Inventors
- 👤 David L. Thompson
- 👤 Donald W. Zobel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:29
CPC Classifications
A; A61; A61N; A61N1/00; A61N1/18; A61N1/32; A61N1/36; A61N1/362; A61N1/365; A61N1/372; A61N1/37211
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
86 words
In a digitally controlled implantable heart pacemaker, a plurality of logic circuits interconnected to perform pacemaker control functions, first bias means for supplying bias current to a first group of said logic circuits, a second bias means for providing a switchable bias current to a second group of said logic circuits, and control means for controlling said second bias means and operative to increase bias current to said second group of logic circuits at selected intervals to increase the switching speed thereof during said selected intervals.
Claim 2
Dependent Claim
86 words
In a digitally controlled implantable heart pacemaker, a plurality of logic circuits interconnected to perform pacemaker control functions, first bias means for supplying bias current to a first group of said logic circuits, a second bias means for providing a switchable bias current to a second group of said logic circuits, and control means for controlling said second bias means and operative to increase bias current to said second group of logic circuits at selected intervals to increase the switching speed thereof during said selected intervals.
Claim 3
Dependent Claim
31 words
Apparatus according to claim 1 wherein said control means is operative to increase said bias current at selected intervals which include the time of the stimulating output pulse of the pacemaker.
Claim 4
Dependent Claim
20 words
Apparatus according to claim 1 wherein said second group of logic circuits comprises pulse width control logic for the pacemaker.
Claim 5
Dependent Claim
57 words
Apparatus according to claim 1 wherein said second bias means switches some of said logic circuits of said second group from a bias off to a bias on condition during said selected intervals, and switches other logic circuits of said second logic group from a low bias to a high bias current condition during said selected intervals.
Claim 6
Dependent Claim
124 words
An integrated injection logic circuit for an implantable heart pacemaker comprising a plurality of logic cells or gates interconnected to perform pacemaker control functions including rate control logic for initiating a pacemaker output pulse at the end of a predetermined escape interval from a previous heart depolarization and pulse width control logic for terminating the pacemaker output pulse at a predetermined pulse duration, bias circuits for supplying bias current to the logic gates, a separate bias circuit for logic gates of the pulse width control logic, and bias switching circuit means connected for increasing bias current to said separate bias circuit upon initiation of a pacemaker output pulse and for reducing bias to said separate bias circuit during escape intervals between pacemaker output pulses.
Claim 7
Dependent Claim
124 words
An integrated injection logic circuit for an implantable heart pacemaker comprising a plurality of logic cells or gates interconnected to perform pacemaker control functions including rate control logic for initiating a pacemaker output pulse at the end of a predetermined escape interval from a previous heart depolarization and pulse width control logic for terminating the pacemaker output pulse at a predetermined pulse duration, bias circuits for supplying bias current to the logic gates, a separate bias circuit for logic gates of the pulse width control logic, and bias switching circuit means connected for increasing bias current to said separate bias circuit upon initiation of a pacemaker output pulse and for reducing bias to said separate bias circuit during escape intervals between pacemaker output pulses.
Claim 8
Dependent Claim
41 words
An integrated injection logic circuit for an implantable heart pacemaker according to claim 5 wherein said bias switching circuit means is operative to increase bias current to said separate bias circuit just prior to the initiation of a pacemaker output pulse.
Claim 9
Dependent Claim
48 words
An integrated injection logic circuit for an implantable heart pacemaker according to claim 5 wherein said bias switching circuit means is operative to switch said bias current between a low value during the escape intervals between pacemaker output pulses and a higher value during the pacemaker output pulse.
Claim 10
Dependent Claim
45 words
An integrated injection logic circuit for an implantable heart pacemaker according to claim 5 wherein said bias switching circuit means is operative to turn said separate bias current off during escape intervals between pacemaker output pulses and to turn it on during pacemaker output pulses.
Claim 11
Dependent Claim
98 words
An integrated injection logic circuit for an implantable heart pacemaker according to claim 5 including a pair of separate bias circuits for supplying bias current to separate groups of logic gates, respectively, within the pulse width control logic, and wherein said bias switching circuit means is connected for increasing the bias current to one of said separate bias circuits from a low bias to a high bias condition during a pacemaker output pulse and for increasing the bias current in the other separate bias circuit from an off condition to an on condition during a pacemaker output pulse.
Claim 12
Dependent Claim
145 words
An implantable heart pacemaker having low power consumption, comprising: terminal means for connection to a patient's heart; pulse generating means connected to said terminal means and operative when activated to deliver output stimulating pulses thereto; rate control means operative to periodically activate said pulse generating means to deliver output stimulation pulses; pulse width control circuitry operative when said pulse generating means is activated to time a preselected output pulse width interval and to thereafter deactivate said pulse generating means to terminate the output stimulating pulse after the preselected duration; and bias control means operatively connected for providing bias current to the individual switching circuits of said pulse width control circuitry at a magnitude to permit high speed switching thereof when said pulse width control circuitry is timing said preselected output pulse width interval, and thereafter to reduce the bias current thereto to reduce power consumption.
Claim 13
Dependent Claim
145 words
An implantable heart pacemaker having low power consumption, comprising: terminal means for connection to a patient's heart; pulse generating means connected to said terminal means and operative when activated to deliver output stimulating pulses thereto; rate control means operative to periodically activate said pulse generating means to deliver output stimulation pulses; pulse width control circuitry operative when said pulse generating means is activated to time a preselected output pulse width interval and to thereafter deactivate said pulse generating means to terminate the output stimulating pulse after the preselected duration; and bias control means operatively connected for providing bias current to the individual switching circuits of said pulse width control circuitry at a magnitude to permit high speed switching thereof when said pulse width control circuitry is timing said preselected output pulse width interval, and thereafter to reduce the bias current thereto to reduce power consumption.
Claim 14
Dependent Claim
31 words
A pacemaker according to claim 10 wherein said bias control means turns off the bias current to some circuits of said pulse width control circuitry after the output pulse width interval.
Claim 15
Dependent Claim
25 words
A pacemaker according to claim 10 wherein said bias control means reduces said bias current to a low magnitude during intervals between output stimulating pulses.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-25 | 1986-10-25 | 1987-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-25 | 1990-10-25 | 1991-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-25 | 1994-10-25 | 1995-04-26 | $7700.00 | Window Closed / Lapsed |