US4380115A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a semiconductor device with a seal
Assignee: Allegro Microsystems LLC
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Filing: 1981-08-17
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Granted: 1983-04-19
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Expires: 2001-08-17
Abstract
Abstract A seal for a semiconductor device in which the semiconductor has a major surface with a metal layer overlying the major surface. An insulating layer of glass is formed on the metal layer and a passive sealing silicon layer is formed on the glass layer for protecting the device from contamination.
Inventors
- 👤 Louis N. Pomante
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:23
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/131; H10W74/147; H10W74/01; Y; Y10; Y10S; Y10S438/00; Y10S438/958
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
149 words
A method of fabricating a semiconductor device comprising the steps of: (a) forming a layer of metal overlying a major surface of a semiconductor body, and removing parts of said metal layer to leave a pattern thereof overlying said semi-conductor surface, (b) forming an insulating passivating layer of silicon dioxide overlying and contacting said patterned metal layer, (c) forming a passive sealing silicon layer overlying and contacting the insulating layer by placing said semi-conductor device with said patterned metal layer and insulating layer formed thereon in a chamber containing an atmosphere including a gas which decomposes and deposits silicon at a temperature below 525° C. for a time duration sufficient to form a deposit of silicon in the range of 500 to 3000 A thick approximately, and (d) etching windows in the sealing silicon layer and insulating layer to provide openings to receive terminal connections to said metal layer.
Claim 2
Independent Claim
149 words
A method of fabricating a semiconductor device comprising the steps of: (a) forming a layer of metal overlying a major surface of a semiconductor body, and removing parts of said metal layer to leave a pattern thereof overlying said semi-conductor surface, (b) forming an insulating passivating layer of silicon dioxide overlying and contacting said patterned metal layer, (c) forming a passive sealing silicon layer overlying and contacting the insulating layer by placing said semi-conductor device with said patterned metal layer and insulating layer formed thereon in a chamber containing an atmosphere including a gas which decomposes and deposits silicon at a temperature below 525° C. for a time duration sufficient to form a deposit of silicon in the range of 500 to 3000 A thick approximately, and (d) etching windows in the sealing silicon layer and insulating layer to provide openings to receive terminal connections to said metal layer.
Claim 3
Dependent Claim
25 words
The method of claim 1 in which step (c) includes forming the sealing silicon layer in a chamber at a temperature of about 475° C.
Claim 4
Dependent Claim
33 words
The method of claim 1 in which step (c) includes forming the sealing silicon layer for a time duration sufficient to provide a thickness in a range of 500 to 1000 A approximately.
Claim 5
Dependent Claim
14 words
The method of claim 1 in which the sealing silicon layer is polycrystalline silicon.
Claim 6
Dependent Claim
20 words
A method of fabricating a sealed semiconductor device, as recited in claim 1, wherein said chamber atmosphere also includes nitrogen.
Claim 7
Dependent Claim
25 words
A method of fabricating a sealed semiconductor device, as recited in claim 1, wherein a second passivating layer is deposited over said sealing silicon layer.
Claim 8
Dependent Claim
22 words
The method of claim 1 in which step (c) includes forming the sealing silicon layer directly on and contacting the passivation layer.
Claim 9
Dependent Claim
27 words
The method of claim 7 in which there is provided the further step of forming an additional passivation layer contacting the sealing silicon layer after step (c).
Claim 10
Independent Claim
140 words
A method of fabricating a seal for a semiconductor device having an electrical circuit thereon, said device including: a patterned layer of metal overlying a major surface of said semiconductor body, said patterned metal layer comprising an active, conductive element of said circuit, said device further including a passivation layer overlying the patterned layer of metal, said method comprising placing said semiconductor device with said metal layer and passivation layer thereon in a chamber containing an atmosphere including silane at a temperature range of 425° C. to 525° C. to deposit, by thermal decomposition of said silane, a silicon layer overlying said passivating layer, said deposited silicon layer being adapted to be passive and inactive in the electrical circuit or field shielding function of the semiconductor device and effective as a seal to preclude intrusion of contaminants into said device.
Claim 11
Independent Claim
140 words
A method of fabricating a seal for a semiconductor device having an electrical circuit thereon, said device including: a patterned layer of metal overlying a major surface of said semiconductor body, said patterned metal layer comprising an active, conductive element of said circuit, said device further including a passivation layer overlying the patterned layer of metal, said method comprising placing said semiconductor device with said metal layer and passivation layer thereon in a chamber containing an atmosphere including silane at a temperature range of 425° C. to 525° C. to deposit, by thermal decomposition of said silane, a silicon layer overlying said passivating layer, said deposited silicon layer being adapted to be passive and inactive in the electrical circuit or field shielding function of the semiconductor device and effective as a seal to preclude intrusion of contaminants into said device.
Claim 12
Dependent Claim
14 words
The method of claim 9 in which the passivation layer is formed of glass.
Claim 13
Dependent Claim
15 words
The method of claim 1 in which step (a) comprises forming a layer of aluminum.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-18 | 1986-10-18 | 1987-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-18 | 1990-10-18 | 1991-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-18 | 1994-10-18 | 1995-04-19 | $7700.00 | Window Closed / Lapsed |