Arithmetic circuit with overflow detection capability

Claim 1

In an arithmetic circuit of the type for performing an arithmetic operation comprising a plurality of consecutive internal addition or subtraction operations, said circuit including a calculating means for receiving first and second inputs represented in two's complement-fixed point and adding or subtracting said inputs to provide an output and accumulator means for receiving and storing said calculating means output, the content of said accumulator means being provided as said second input and said first input being externally supplied, whereby said arithmetic circuit performs consecutive additions or subtractions in response to consecutive externally supplied first inputs, said circuit further comprising: overflow occurrence detection means for providing an overflow occurrence signal output each time an overflow occurs in one of said internal operations; overflow direction detection means for providing an overflow direction signal output indicating the direction of each said overflow; and overflow monitoring means responsive to said overflow occurrence and overflow direction signals for offsetting positive and negative overflows against one another, said overflow monitoring means providing a net overflow occurrence signal and a net overflow direction signal indicating the occurrence and direction of a net overflow if an unequal number of positive and negative overflows has occurred during said arithmetic operation, said overflow monitoring means providing no net overflow occurrence signal if an even number of alternately occurring positive and negative overflows has occurred during said arithmetic operation.