Modular system controller for a transition machine

Claim 2

A modular hardware executive apparatus for use in a multiprocessing system for concurrent operation of a plurality of data processors for solving computational problems defined by a plurality of application programs and a control program, said data processors connected for accessing said plurality of application programs stored in application program memory storage means and data stored in data memory storage means including at least a common data memory area accesible by said plurality of data processors, said plurality of data processors generating variable status indications upon execution of said application programs said hardware executive apparatus connected to said plurality of data processors and executing said control program and comprising: (a) at least one status storage means for storing status indications S j corresponding to data conditions defined on elements of a data set appropriate for determining eligibility of said application programs, whereby said stored status indications correspond to data conditions which are relevant for enabling execution of application programs by said plurality of processors which are utilized in solving said computational problems; (b) a plurality of modular units, each unit including a relevance storage means for storing groups of relevance indications R ij each group corresponding to the relevance of at least some of said status indications to at least one of said application programs where i is an integer designating one of said groups and corresponding one of said application programs and j is an integer designating one of said status indications; (c) means connected to said status storage means and connected to receive said variable status indications from said data processors, and responsive to said variable status indications for updating said status indications stored in said status storage means at the completion of execution of said application program each of said variable status indications having a given value corresponding to and indicating satisfaction of a given one of said data conditions, said given data conditions being logical relationships involving at least one element of said data set being determined by said data processors upon execution of said application programs, said updating means including means for modifying a plurality of said status indications upon execution of at least one of said application programs; (d) means connected to at least two of said relevance storage means and said at least one status storage means for determining the eligibility of at least some of said application programs for execution by said plurality of processors; and (e) means responsive to said eligibility determining means and operatively connected to said data processors for enabling execution of eligible application programs by said plurality of data processors whereby at least some of said application programs which are determined eligible may be executed concurrently.

Claim 3

A hardware executive apparatus as recited in claim 1, wherein said data processors solve a plurality of disjoint computational problems, said disjoint computational problems defined by different groups of application programs, and wherein said relevance storage means of each modular unit stores relevance indications associated with a different group of application programs.

Claim 4

A hardware executive apparatus as recited in claim 2, wherein said at least one status storage means comprises a plurality of separate status storage means, said updating means comprises a plurality of separate updating means, said eligibility determining means comprises a plurality of separate eligibility determining means and said execution enabling means comprises a plurality of separate execution enabling means, each modular unit further including one of said plurality of separate status storage means, one of said plurality of separate updating means, one of said plurality of separate eligibility determining means and one of said plurality of separate execution enabling means, wherein each modular unit forms a separate hardware executive apparatus for a different group of application programs.

Claim 5

A hardware executive apparatus as recited in claim 3, wherein each of said separate status storage means comprises a status register having bit storage positions corresponding to status indications on a different, disjoint data set corresponding to said different groups of application programs.

Claim 6

A hardware executive apparatus as recited in claim 4, wherein each bit storage position of each of said status storage registers corresponds to one status indication.

Claim 7

A hardware executive apparatus as recited in claim 4, further comprising a plurality of interface controllers, one interface controller connected between each modular unit and said plurality of data processors, each interface controller comprising groups of interface registers, each group of interface registers connected to one of said plurality of data processors and comprising: (a) an application program designation address register for storing an application program designation address for an application program determined to be eligible, and (b) an index register for storing application program identifying data for said eligible application programs.

Claim 8

A hardware executive apparatus as recited in claim 4, wherein each of said relevance storage means comprises a relevance matrix storage means wherein each of said groups, i, form rows (columns) of said matrix storage means and individual relevance indications form columns (rows) of said matrix, each column (row) corresponding to one of said status indications on said data set.

Claim 9

A hardware executive apparatus as recited in claim 7, wherein for any given modular unit, said separate means for determining the eligibility of application program i comprises means for multiplying each status indication S j stored in said status storage register of said given modular unit and each corresponding relevance indication R ij stored in said relevance matrix storage means of said given modular unit to form a given logic state.

Claim 10

A hardware executive apparatus as recited in claim 8, wherein each of said application program eligibility determining means further comprises logic means for requiring the results of each multiplication to be a predetermined logic state, whereby in said given modular unit, application program i is eligible if all status indications S j in said given modular unit corresponding to relevance indications R ij are in said predetermined logic state.

Claim 11

A hardware executive apparatus as recited in claim 9, wherein, in said given modular unit, said means for updating said status indications comprises: (a) means responsive to said data processors for sensing the completion of execution of each application program i of said given modular unit; (b) means for storing fixed status indications (T,F) associated with each application program i, of said given modular unit, said fixed status indications determined by a given one of said computational problems independently of values of said associated data set; (c) means for storing said variable status indications received from said data procesors; and (d) said means for modifying including logic circuit means responsive to said stored status indications, said stored fixed status indications and said variable status indications for generating update status indications said logic circuit means connected to said status storage means for storage of said update status indications in said status storage means of said given modular unit.

Claim 12

A hardware executive apparatus as recited in claim 10, wherein said fixed status indications (T,F) are stored in a matrix storage means, each row (column) thereof corresponding to one of said application programs of said given modular unit, and each column (row) thereof corresponding to one of said status indications S j of said given modular unit, and said means for storing said variable status indications comprises a storage register V having bit positions corresponding to said status indications of said status storage means.

Claim 13

A hardware executive apparatus as recited in claim 11, wherein said means for enabling execution of said eligible application programs comprises a plurality of application program designation address storage means for defining designation addresses for execution of eligible application programs, and a plurality of data access pointers corresponding to each of said application programs.

Claim 14

A hardware executive apparatus as recited in claim 12, wherein said application program designation address storage means comprises storage registers.

Claim 15

A hardware executive apparatus as recited in claim 13, wherein said apparatus further comprises an index register for storing application program identification data, said updating means of said given modular unit responsive to said application program identification data of said index register for identifying said application program i of said given modular unit.

Claim 16

A hardware executive apparatus as recited in claim 12, further comprising a plurality of interface controllers, one interface controller connected between each modular unit and said plurality of data processors, each interface controller comprising groups of interface registers, each group of interface registers connected to one of said plurality of data processors and comprising: (a) an application program designation address register for storing an application program designation address from said associated application program designation address storage means for an application program determined to be eligible, and (b) an index register for storing application program identifying data for said eligible application programs.

Claim 17

A hardware executive apparatus as recited in claim 15, wherein each group of interface registers further comprises a data register for storing said data access pointers for eligible application programs.

Claim 18

A hardware executive apparatus as recited in claim 16, wherein each group of interface registers further comprises: fixed status registers for loading said fixed status indications into said fixed status indication storing means of said associated modular unit, and a variable status register for loading said variable status indications into said variable status indication storing means of said associated modular unit.

Claim 19

A computing system for solving a plurality of disjoint computational problems, each said disjoint computation problem solved by execution of a plurality of application programs and a control program, said system comprising: (a) a plurality of data processors connected for accessing application program memory storage means storing said application programs and data memory storage means storing data elements, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors and at least one of said plurality of data processors including means for generating at least one variable status indication determined upon execution of at least one of said plurality of application programs; (b) a plurality of system controller modular units, each unit operable for execution of one of said control programs for controlling execution of application programs corresponding to a different one of said disjoint computational problems, each unit including: (1) a status register for storing status indications S j of a plurality of data conditions appropriate for said one of said disjoint computational problems; (2) a relevance matrix store for storing indications R ij of the relevance of each data condition j to each application program i of said corresponding plurality of application programs; (3) means connected to said status register and responsive to said at least one variable status indication for updating said status indications of said status register said at least one variable status indication indicating satisfaction of a data condition, said data condition being a logical relationship involving at least one of said data elements, said at least one data element having a value determined by said at least one data processor upon execution of said at least one application program, said updating means including means for modifying a plurality of said status indications in response to execution of one of said applications; (4) means for storing a plurality of application program designation addresses corresponding to each application program; (5) means responsive to said status indications of said status register, said corresponding relevance indications of said relevance matrix store and said application program designation addresses of said application program designation storing means for determining the eligibility of each application program for execution by said plurality of data processors and for generating designation addresses from said application program designation address storage means for application programs determined to be eligible, wherein eligible programs are executed concurrently in said plurality of data processors; and (6) synchronization and control logic means for synchronizing and controlling operation of said system controller modular unit; whereby said system controller modular units form a hardware executive apparatus for said computing system; and (c) interface means connected between said plurality of data processors and said plurality of system controller modular units.

Claim 20

A computing system for solving a plurality of disjoint computational problems, each said disjoint computation problem solved by execution of a plurality of application programs and a control program, said system comprising: (a) a plurality of data processors connected for accessing application program memory storage means storing said application programs and data memory storage means storing data elements, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors and at least one of said plurality of data processors including means for generating at least one variable status indication determined upon execution of at least one of said plurality of application programs; (b) a plurality of system controller modular units, each unit operable for execution of one of said control programs for controlling execution of application programs corresponding to a different one of said disjoint computational problems, each unit including: (1) a status register for storing status indications S j of a plurality of data conditions appropriate for said one of said disjoint computational problems; (2) a relevance matrix store for storing indications R ij of the relevance of each data condition j to each application program i of said corresponding plurality of application programs; (3) means connected to said status register and responsive to said at least one variable status indication for updating said status indications of said status register said at least one variable status indication indicating satisfaction of a data condition, said data condition being a logical relationship involving at least one of said data elements, said at least one data element having a value determined by said at least one data processor upon execution of said at least one application program, said updating means including means for modifying a plurality of said status indications in response to execution of one of said applications; (4) means for storing a plurality of application program designation addresses corresponding to each application program; (5) means responsive to said status indications of said status register, said corresponding relevance indications of said relevance matrix store and said application program designation addresses of said application program designation storing means for determining the eligibility of each application program for execution by said plurality of data processors and for generating designation addresses from said application program designation address storage means for application programs determined to be eligible, wherein eligible programs are executed concurrently in said plurality of data processors; and (6) synchronization and control logic means for synchronizing and controlling operation of said system controller modular unit; whereby said system controller modular units form a hardware executive apparatus for said computing system; and (c) interface means connected between said plurality of data processors and said plurality of system controller modular units.

Claim 21

A general purpose computing machine as recited in claim 1 or 18 wherein said application programs are event-driven data transformation programs without direct transfer of control therein or to other application programs.

Claim 22

A general purpose computing machine as recited in claim 18 wherein said system controller modular units are operable for determining eligibility based on a plurality of unary predicates associated with the applicability of the transitions between states of said machine for solving said algorithm.

Claim 23

A computing system as recited in claim 18, wherein said interface means comprises a plurality of interface controllers, one interface controller connected between each modular unit and said plurality of data processors, each interface controller comprising groups of interface registers, each group of interface registers connected to one of said plurality of data processors and comprising: (a) an application program designation address register for storing an application program designation address from said associated application program designation address storage means for an application program determined to be eligible, and (b) an index register for storing application program identifying data for said eligible application programs.

Claim 24

A computing system as recited in claim 21, wherein: each group of interface registers comprises a type register for storing indications of the processor type requesting access to said system controller modular unit; each of said system controller modular units further comprises a plurality of processor type storage means corresponding to each application program i, said processor type storage means storing indications of the type of data processor appropriate for executing said corresponding application program i; and said means for determining eligibility of each application program i comprising means for comparing indications of the data processor type stored in said interface type register with said indications of said data processor type stored in said processor type storage means; whereby said plurality of application programs may be executed by specific types of said plurality of data processors.

Claim 25

A computing system as recited in claim 22, wherein said means for determining the eligibility of each application program i further comprises: (a) means for forming a logical operation with each status indications S j and each corresponding relevance indication R ij to form a logic state; and (b) logic means for requiring each of said logic operations to be in a predetermined logic state such that application program i is eligible if all status indications S j corresponding to said relevant indications R ij are in said predetermined logic state, and said processor requesting access to said system controller is of the type appropriate for executing said application program.

Claim 26

A computing system as recited in claim 23, wherein said relevance matrix store comprises sequentially stored groups i of binary relevance indications R ij and said synchronization and control logic means sequentially select groups of indications of said relevance matrix store for feeding same to said eligibility determining means.

Claim 27

A computing system as recited in claim 24, further comprising means for preventing execution of the same application program in more than one of said plurality of data processors at the same time.

Claim 28

A computing system as recited in claim 25, wherein said execution preventing means comprises means for providing a predetermined status indication S j in said status register corresponding to those status indications utilized in determining eligibility of an application program currently being executed, whereby other application programs utilizing said predetermined status indications are not determined eligible by said eligibility determining means.

Claim 29

A modular computing system comprising: (a) a plurality of data processors connected for accessing application program memory storage means storing application programs and data memory storage means storing data, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors said plurality of data processors including means for computing data in accordance with said application programs and means for generating at least one variable status indication corresponding to other than a program termination event and representing satisfaction of at least one data condition dependent upon at least one non-predetermined value of data processed by said data processing means; (b) a plurality of Z modular units, each modular unit including: (1) a status register for storing M binary status indications of M data conditions appropriate for partially determining the eligibility of said application programs stored in said application program memory storage means, Z and M being integers, at least one status register of at least one modular unit storing said variable status indication received from at least one of said data processors; (2) a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of said application programs; and (3) means connected to said status register for updating said M binary status indications of said status register at least one updating means of at least one modular unit connected to receive said variable status indication; (c) means for storing a plurality of application program designation addresses corresponding to said application programs; (d) means connected to said relevance matrix stores and said status registers for determining the eligibility of said application programs for execution by said plurality of data processors, said eligibility determining means responsive to said ZM binary status indications of said Z status registers and said corresponding ZM binary relevance indications of said Z relevance matrix stores; (e) logic circuit means for synchronizing and controlling said modular units, for scheduling execution of said application programs, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation address for application programs determined to be eligible; and (f) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and whereby Z modular units may be utilized in said computing system for increasing the number of data conditions for a computational problem to be solved by said computing system.

Claim 30

A modular computing system comprising: (a) a plurality of data processors connected for accessing application program memory storage means storing application programs and data memory storage means storing data, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors said plurality of data processors including means for computing data in accordance with said application programs and means for generating at least one variable status indication corresponding to other than a program termination event and representing satisfaction of at least one data condition dependent upon at least one non-predetermined value of data processed by said data processing means; (b) a plurality of Z modular units, each modular unit including: (1) a status register for storing M binary status indications of M data conditions appropriate for partially determining the eligibility of said application programs stored in said application program memory storage means, Z and M being integers, at least one status register of at least one modular unit storing said variable status indication received from at least one of said data processors; (2) a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of said application programs; and (3) means connected to said status register for updating said M binary status indications of said status register at least one updating means of at least one modular unit connected to receive said variable status indication; (c) means for storing a plurality of application program designation addresses corresponding to said application programs; (d) means connected to said relevance matrix stores and said status registers for determining the eligibility of said application programs for execution by said plurality of data processors, said eligibility determining means responsive to said ZM binary status indications of said Z status registers and said corresponding ZM binary relevance indications of said Z relevance matrix stores; (e) logic circuit means for synchronizing and controlling said modular units, for scheduling execution of said application programs, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation address for application programs determined to be eligible; and (f) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and whereby Z modular units may be utilized in said computing system for increasing the number of data conditions for a computational problem to be solved by said computing system.

Claim 31

A modular computing system as recited in claim 27 further comprising: a processor type storage means for storing indications of the type of data processor appropriate for executing each application program; and wherein said interface means comprises a type register for storing indications of the processor type requesting access to said application programs; said means for determining eligibility of said application programs further comprises means for comparing indications of the data processor type stored in said interface type register with said indications of said data processor type stored in said processor type storage means: whereby said plurality of application programs may be executed by specific types of said plurality of data processors.

Claim 32

A modular computing system as recited in claim 27 wherein each relevance matrix store comprises sequentially stored groups of binary relevance indications R ij , each group corresponding to an i th one of said application programs, and said control and control logic circuit means sequentially selects groups of indications of said relevance matrix store for feeding same to said eligibility determining means.

Claim 33

A modular computing system as recited in claim 29 wherein said logic circuit means is operable for restarting said sequential selection of said stored groups of binary relevance indications after an application program is determined eligible by said eligibility determining means, whereby the order of said storage of said binary indications in said relevance matrix store provides a priority selection mechanism for said application programs.

Claim 34

A modular computing system as recited in claim 27 further comprising means for preventing execution of the same application program in more than one of said plurality of data processors at the same time.

Claim 35

A modular computing system as recited in claim 31 wherein said execution preventing means comprises means for providing a false status indications S j corresponding to those status indications required true for eligibility of an application program currently being executed, whereby said application programs currently being executed may not be determined eligible by said eligibility determining means.

Claim 36

A modular computing system as recited in claim 27, wherein said eligibility determining means comprises: (a) a procedure eligibility determination circuit for each modular unit, each of said circuits providing a component eligibility output signal in response to the associated M binary status indications and M binary relevance indications of each of said application programs; and (b) means responsive to said component eligibility output signals from each modular unit for providing an eligibility determination signal whereby said eligibility determination signal is responsive to said ZM binary status indications and said ZM binary relevance indications for each of said application programs, and wherein said synchronization and control logic circuit means is operative in response to said eligibility determination signal for enabling generation of said designation addresses.

Claim 37

A modular computing system as recited in claim 33 further comprising means for storing an application program type indication associated with each of said application programs stored in said application program memory storage means and wherein said eligibility determining means further comprises a comparison circuit for comparing the type of processor seeking access to said application programs with the stored application program type designation and for providing an additional component eligibility output signal, said eligibility determination signal means responsive to said additional component eligibility output signal for providing said eligibility determination signal.

Claim 38

A modular computing system as recited in claim 33 wherein said procedure eligibility determination circuit for each modular unit comprises means for forming a logical operation with each of said associated M binary status indications and each corresponding M binary relevance indications for each of said application programs such that said component eligibility output signal is provided only if the results of all of said logical operations are a predetermined logic state, and said means for providing said eligibility determination signal comprises means for logically combining said component eligibility output signals such that said eligibility determination signal is provided only if all of said component eligibility output signals are in said predetermined logic state.

Claim 39

A modular computing system as recited in claim 27 or 35, wherein said interface means comprises: (a) an execute register for storing said application program designation addresses; and (b) an index register for storing identifying representations of application programs at the completion of execution by said data processors.

Claim 40

A modular computing system as recited in claim 36, wherein said interface means further comprises a busy/not busy binary indicator register for indicating whether the modular units are busy/not busy upon request for access by said data processors.

Claim 41

A modular computing system as recited in claim 36, wherein said interface means comprises a multiport controller and a plurality of execute, and index registers corresponding to said plurality of data processors.

Claim 42

A modular computing system as recited in claim 36, wherein said interface means comprises a binary mode indication register (X) loaded by said data processors for identifying entry and exit modes of operation: said system operable in said entry mode of operation in response to loading of said mode indication register by the k th one of said plurality of data processors for determining eligibility of the i th one of said application programs for execution by said k th data processor and for generating an application program designation address corresponding to said i th application program for storage in said execute register of said interface means for loading by said k th data processor whereby said k th data processor executes said i th application program; and said system operable in said exit mode in response to loading of said mode indication register by said k th data processor for receiving application program identifying data of said i th application program loaded by said k th data processor into said index register of said interface means for enabling said updating means to update said status register, wherein k is an integer designating one of said data processors and i is an integer designating one of said application programs.

Claim 43

A modular computing system as recited in claim 39, wherein each modular unit further comprises: means for storing fixed status modifying indications (T,F) for modifying said status register upon completion of execution of said i th application program, said fixed status modifying indications determined by said computational problem to be solved independent of data values computed in said k th data processor; and said interface means further comprises means for storing said variable status indications (V) associated with completion of said i th application program, each of said updating means receiving said fixed status indications and said variable status indications for determining updated binary status indications of said data conditions and for storing same in each of said status registers.

Claim 44

A modular computing system as recited in claim 40, wherein said interface means further comprises means for storing said fixed status indications for loading into said fixed status indications storing means of each modular unit.

Claim 45

A modular computing system comprising: (a) a plurality of data processors accessing application program memory storage means storing application programs and data memory storage means storing data, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors said plurality of data processors including means for computing data in accordance with said application programs and means for generating at least one variable status indication corresponding to other than a program termination event and representing satisfaction of at least one data condition dependent upon at least one non-predetermined value of data processed by said data processing means; (b) a system controller comprising: (1) a status register for storing M binary status indications of a plurality of M data conditions appropriate for determining the eligibility of up to ZN application programs stored in said application program memory storage means, Z, M and N being integers and N being less than the number of application programs stored in said application program memory storage means and utilized for solving a computational problem by said computing system, (2) a plurality of Z modular units, each modular unit including: (i) a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of as many as N application programs, said relevance indications being different from one modular unit to another and corresponding to different groups of application programs, each group having as many as N application programs; (ii) means connected to said status register for updating said binary status indications of said status register at least one updating means of at least one modular unit connected to receive said variable status indication for updating said binary status indications in response thereto; and (iii) means for storing up to ZN application program designation addresses corresponding to said application programs; and (3) means connected to said relevance matrix stores and said status register for determining the eligibility of said up to ZN application programs for execution by said plurality of data processors, said eligibility determining means responsive to said M binary status indications of said status register and said M corresponding binary relevance indications of said relevance matrix store; (4) logic circuit means for synchronizing and controlling said modular units, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation addresses for application programs determined to be eligible; and (c) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and whereby any number of Z modular units may be utilized in said computing system for increasing the number of application programs utilized for solving a computational problem by said computing system.

Claim 46

A modular computing system comprising: (a) a plurality of data processors accessing application program memory storage means storing application programs and data memory storage means storing data, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors said plurality of data processors including means for computing data in accordance with said application programs and means for generating at least one variable status indication corresponding to other than a program termination event and representing satisfaction of at least one data condition dependent upon at least one non-predetermined value of data processed by said data processing means; (b) a system controller comprising: (1) a status register for storing M binary status indications of a plurality of M data conditions appropriate for determining the eligibility of up to ZN application programs stored in said application program memory storage means, Z, M and N being integers and N being less than the number of application programs stored in said application program memory storage means and utilized for solving a computational problem by said computing system, (2) a plurality of Z modular units, each modular unit including: (i) a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of as many as N application programs, said relevance indications being different from one modular unit to another and corresponding to different groups of application programs, each group having as many as N application programs; (ii) means connected to said status register for updating said binary status indications of said status register at least one updating means of at least one modular unit connected to receive said variable status indication for updating said binary status indications in response thereto; and (iii) means for storing up to ZN application program designation addresses corresponding to said application programs; and (3) means connected to said relevance matrix stores and said status register for determining the eligibility of said up to ZN application programs for execution by said plurality of data processors, said eligibility determining means responsive to said M binary status indications of said status register and said M corresponding binary relevance indications of said relevance matrix store; (4) logic circuit means for synchronizing and controlling said modular units, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation addresses for application programs determined to be eligible; and (c) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and whereby any number of Z modular units may be utilized in said computing system for increasing the number of application programs utilized for solving a computational problem by said computing system.

Claim 47

A modular computing system as recited in claim 42, wherein said means for determining eligibility of said up to ZN application programs comprises a procedure eligibility determination logic circuit for each modular unit, each procedure eligibility determination logic circuit providing a component eligibility output signal and said system controller further comprising: a priority selection circuit responsive to said component eligibility output signals for enabling said synchronization and control logic circuit means to generate an application program designation address and for generating module selection signals corresponding to a selected modular unit, and multiplexing means connected between said interface means and said plurality of modular units and responsive to said module selection signals for feeding application program designation addresses from said selected modular unit to said interface means.

Claim 48

A modular computing system as recited in claim 43, wherein said interface means comprises: (a) an execute register for storing application program designation addresses, and (b) an index register for storing indentifying representations of modular units and application programs controlled by said modular units.

Claim 49

A modular computing system as recited in claim 44, wherein said interface means comprises a binary mode indication register (X) loaded by said data processors for identifying entry and exit modes of operation: said system operable in said entry mode of operation in response to loading of said mode indication register by the k th one of said plurality of data processors for determining eligibility of the i th one of said application programs for execution by said k th data processor and for generating an application program designation address corresponding to said i th application program for storage in said execute register of said interface means for loading by said k th data processor whereby said k th data processor executes said i th application program; and said system operable in said exit mode in response to loading of said mode indication register by said k th data processor for receiving application program identifying data of said i th application program loaded by said k th data processor into said index register of said interface means for enabling said updating means to update said status register, wherein k is an integer designating one of said data processors and i is an integer designating one of said application programs.

Claim 50

A modular computing system as recited in claim 45, wherein each modular unit further comprises: means for storing fixed status indications (T,F) for said status register upon completion of execution of said i th application program, said fixed status indications determined by said computational problem to be solved independent of data values computed in said k th data processor; and each of said updating means receiving said fixed status indications and said at least one variable status indications of said data conditions and storing same said status register.

Claim 51

A modular computing system as recited in claim 46, wherein said interface means further comprises means for storing said fixed status modifying indications for loading into said fixed status modifying indications storing means of each modular unit.