Composite video signal separator

Claim 2

A composite video signal separator comprising, in combination: an input terminal adapted for receiving a composite video signal, said composite video signal having therein a horizontal sync component, a vertical sync component, and a video component; first separating means having an input connected to said input terminal, and an output for passing therethrough the video component of said composite video signal, for amplifying the video component of said composite video signal, and for inverting the video component of said composite video signal so as to provide at the output thereof a video signal; second separating means having an input connected to said input terminal and an output for passing therethrough the horizontal sync and vertical sync components of said composite video signal, for amplifying the horizontal sync and vertical sync components of said composite video signal, and for inverting the horizontal sync and vertical sync components of said composite video signal; first phase lock loop circuit means having a data input connected to the output of said second separating means and an output for locking in upon the vertical sync component of said composite video signal so as to provide at the output thereof a vertical sync signal, said vertical sync signal having therein a plurality of vertical sync pulses; second phase lock loop circuit means having a data input connected to the output of said second separating means, first and second control inputs, and an output for locking in upon the horizontal sync component of said composite video signal so as to provide at the output thereof a horizontal sync signal, said horizontal sync signal having therein a plurality of horizontal sync pulses; first one-shot multivibrator means having a data input connected to the output of said first phase lock loop circuit means and an output for expanding the pulse width of each pulse of said vertical sync signal; and second one-shot multivibrator means having a data input connected to the output of said second phase lock loop circuit means, first and second control inputs, and an output for expanding the pulse width of each pulse of said horizontal sync signal.

Claim 3

The composite video signal separator of claim 1, wherein said first separating means comprises: an operational amplifier having an input and an output, with the input thereof connected to said input terminal; and a diode having an anode and a cathode, with the anode thereof connected to the output of said operational amplifier and the cathode thereof connected to the input of said operational amplifier.

Claim 4

The composite video signal separator of claim 1 wherein said second separating means comprises: an operational amplifier having an input and an output, with the input thereof connected to said input terminal; and a diode having an anode and a cathode, with the anode thereof connected to the input of said operational amplifier and with the cathode thereof connected to the output of said operational amplifier.

Claim 5

The composite video signal separator of claim 1 further characterized by: a transistor having an emitter, a base, and a collector, with the emitter thereof connected to the output of said first separating means, the collector thereof connected to the input of said first separating means, and the base thereof effectively connected to said input terminal; and the parallel combination of a resistor and a capacitor connected between said input terminal and the base of said transistor.

Claim 6

The composite video signal separator of claim 4 wherein said transistor is a PNP transistor.

Claim 7

The composite video signal separator of claim 1 further characterized by: a direct current voltage source having an output connected to the second control input of said one-shot multivibrator means; a ground; and a double pole double throw switch having a first input connected to said ground, a second input connected to the output of said direct current voltage source, a first output connected to the first control input of said second phase lock loop circuit means, a second output connected to the second control input of said second phase lock loop circuit means, a third output connected to the first control input of said second one-shot multivibrator means.

Claim 8

The composite video signal separator of claim 6 further characterized by: a first NAND gate having a first input connected to the output of said first one-shot multivibrator means, a second input connected to the output of said direct current voltage source and an output; a second NAND gate having a first input connected to the output of said first NAND gate, a second input connected to the output of said second one-shot multivibrator means, and an output; and a third NAND gate having a first input connected to the output of said second NAND gate, and a second input connected to the output of said direct current voltage source.

Claim 9

A circuit for separating horizontal and vertical sync signals and a video signal from a composite video signal comprising, in combination: an input terminal; a transistor having an emitter, a base, and a collector, with the base thereof connected to said input terminal; a first operational amplifier having an input and an output, with the input thereof effectively connected to said input terminal and the collector of said transistor, and with the output thereof connected to the emitter of said transistor; a first diode having an anode and a cathode, with the anode thereof connected to the emitter of said transistor and with the cathode thereof connected to the collector of said transistor; a second operational amplifier having an input and an output, with the input thereof effectively connected to said input terminal; a second diode having an anode and a cathode, with the anode thereof connected to the input of said second operational amplifier and the cathode thereof connected to the output of said second operational amplifier. a first phase lock loop circuit having a data input connected to the output of said second operational amplifier and an output; a first one-shot multivibrator having a data input connected to the output of said first phase lock loop circuit and an output; a second phase lock loop circuit having a data input, first and second control inputs, and an output, with the data input thereof connected to the output of said second operational amplifier; a second one-shot multivibrator having a data input, first and second control inputs, and an output, with the data input thereof connected to the output of said second phase lock loop circuit; a direct current voltage source having an output connected to the second control input of said second one-shot multivibrator; a ground; a double pole double throw switch having a first input connected to said ground, a second input connected to the output of said direct current voltage source, a first output connected to the first control input of said second phase lock loop circuit, a second output connected to the second control input of said second phase lock loop circuit, and a third output connected to the first control input of said second one-shot multivibrator; and first, second and third output terminals, the first of which is connected to the output of said first operational amplifier, the second of which is connected to the output of said first one-shot multivibrator, and the third of which is connected to the output of said second one-shot multivibrator.

Claim 10

A circuit for separating horizontal and vertical sync signals and a video signal from a composite video signal comprising, in combination: an input terminal; a transistor having an emitter, a base, and a collector, with the base thereof connected to said input terminal; a first operational amplifier having an input and an output, with the input thereof effectively connected to said input terminal and the collector of said transistor, and with the output thereof connected to the emitter of said transistor; a first diode having an anode and a cathode, with the anode thereof connected to the emitter of said transistor and with the cathode thereof connected to the collector of said transistor; a second operational amplifier having an input and an output, with the input thereof effectively connected to said input terminal; a second diode having an anode and a cathode, with the anode thereof connected to the input of said second operational amplifier and the cathode thereof connected to the output of said second operational amplifier. a first phase lock loop circuit having a data input connected to the output of said second operational amplifier and an output; a first one-shot multivibrator having a data input connected to the output of said first phase lock loop circuit and an output; a second phase lock loop circuit having a data input, first and second control inputs, and an output, with the data input thereof connected to the output of said second operational amplifier; a second one-shot multivibrator having a data input, first and second control inputs, and an output, with the data input thereof connected to the output of said second phase lock loop circuit; a direct current voltage source having an output connected to the second control input of said second one-shot multivibrator; a ground; a double pole double throw switch having a first input connected to said ground, a second input connected to the output of said direct current voltage source, a first output connected to the first control input of said second phase lock loop circuit, a second output connected to the second control input of said second phase lock loop circuit, and a third output connected to the first control input of said second one-shot multivibrator; and first, second and third output terminals, the first of which is connected to the output of said first operational amplifier, the second of which is connected to the output of said first one-shot multivibrator, and the third of which is connected to the output of said second one-shot multivibrator.

Claim 11

The circuit of claim 9 wherein said transistor is a PNP transistor.

Claim 12

The circuit of claim 8 further characterized by the parallel combination of a resistor and a capacitor connected between said input terminal and the base of said transistor.

Claim 13

The circuit of claim 8 further characterized by: a first NAND gate having a first input connected to said second output terminal, a second input connected to the output of said direct current voltage source, and an output; a second NAND gate having a first input connected to the output of said first NAND gate, a second input connected to said third output terminal, and an output; and a third NAND gate having a first input connected to the output of said second NAND gate, and a second input connected to the output of said direct current voltage source.