US4376898A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Back bias regulator
Assignee: EMC Corp
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Filing: 1980-02-29
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Granted: 1983-03-15
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Expires: 2000-02-29
Abstract
Abstract An improved regulator circuit alters the back bias generator voltage at the substrate of an MOS integrated circuit. The regulator circuit is responsive not only to circuit parameters sensed by prior art regulators, but to additional ones including internal clock pulse voltage levels.
Inventors
- 👤 Richard Z. Desmarais
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:53
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
133 words
In an MOS integrated circuit with switching performance controlled by the presence of specified circuit parameters including internal circuit clock pulses, and having a generator to back bias the integrated circuit substrate, an improved back bias generator regulator circuit comprising: regulator means for providing a regulating signal to produce a back bias substrate signal to offset any adverse influence of changing circuit parameters on the switching performance of said MOS integrated circuit; sensing means responsive to internal circuit clock pulses within the MOS integrated circuit substrate for providing a sense signal; means for storing the sense signal as a d.c. level; and means for providing a signal to said regulator means to regulate the back bias voltage if the stored sense voltage fails to reach a specified level in one clock pulse period.
Claim 2
Dependent Claim
133 words
In an MOS integrated circuit with switching performance controlled by the presence of specified circuit parameters including internal circuit clock pulses, and having a generator to back bias the integrated circuit substrate, an improved back bias generator regulator circuit comprising: regulator means for providing a regulating signal to produce a back bias substrate signal to offset any adverse influence of changing circuit parameters on the switching performance of said MOS integrated circuit; sensing means responsive to internal circuit clock pulses within the MOS integrated circuit substrate for providing a sense signal; means for storing the sense signal as a d.c. level; and means for providing a signal to said regulator means to regulate the back bias voltage if the stored sense voltage fails to reach a specified level in one clock pulse period.
Claim 3
Dependent Claim
78 words
A circuit for regulating the back bias voltage at the substrate of an MOS integrated circuit comprising: means sensitive to changing circuit conditions of insufficient levels of internal clock signals to provide a sense signal; means for storing the sense signal; and means responsive to said stored sense signal to provide a regulating signal to alter the back bias voltage depending upon the level of the stored sense signal within the period of time of one clock pulse.
Claim 4
Dependent Claim
78 words
A circuit for regulating the back bias voltage at the substrate of an MOS integrated circuit comprising: means sensitive to changing circuit conditions of insufficient levels of internal clock signals to provide a sense signal; means for storing the sense signal; and means responsive to said stored sense signal to provide a regulating signal to alter the back bias voltage depending upon the level of the stored sense signal within the period of time of one clock pulse.
Claim 5
Dependent Claim
122 words
A back bias generator regulating circuit for an MOS integrated circuit comprising: a sensing circuit responsive to internal clock signals to provide a sense signal having a level dependent upon circuit conditions; an inverter circuit comprising pull-up and pull-down transistors responsive to said sense signal, said inverter circuit being more sensitive than other inverter circuits in the MOS integrated circuit; means for storing the sense signal as a d.c. level; regulator means for providing a signal to alter the magnitude of the back bias voltage; and means responsive to said stored d.c. signal for providing a signal to said regulator means to regulate the back bias voltage if the stored sense voltage fails to reach a specified level in one clock pulse.
Claim 6
Dependent Claim
122 words
A back bias generator regulating circuit for an MOS integrated circuit comprising: a sensing circuit responsive to internal clock signals to provide a sense signal having a level dependent upon circuit conditions; an inverter circuit comprising pull-up and pull-down transistors responsive to said sense signal, said inverter circuit being more sensitive than other inverter circuits in the MOS integrated circuit; means for storing the sense signal as a d.c. level; regulator means for providing a signal to alter the magnitude of the back bias voltage; and means responsive to said stored d.c. signal for providing a signal to said regulator means to regulate the back bias voltage if the stored sense voltage fails to reach a specified level in one clock pulse.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-03-14 | 1986-09-13 | 1987-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-03-14 | 1990-09-13 | 1991-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-03-14 | 1994-09-13 | 1995-03-15 | $7700.00 | Window Closed / Lapsed |