Low voltage serial to parallel to serial charge coupled device

Claim 1

A serial to parallel to serial charge coupled device shift register memory of the type having a plurality of channels in a semiconductor substrate with transfer diodes positioned thereover activated by a series of sequential transfer pulses for transfer of data in the form of charge packets along the parallel channel to form parallel shift registers and additional channel for a single serial shift register at the output ends of said plurality of parallel channels, comprising, a plurality of gate electrodes of two different lengths overlying the channel of said serial register with the longer electrodes also overlying the ends every other of the plurality of channels for said parallel shift registers and the shorter gate electrodes positioned between each two longer electrodes at the end of the intervening channels for the parallel registers, a single gate electrode overlying all of the channels of said parallel shift register adjacent to said plurality of said gate electrodes and having extensions juxtaposed between said longer electrodes and facing said shorter electrodes, said single gate electrode being activated by one of said series of sequential pulses, and transfer electrode means overlying said longer of the plurality of gate electrodes and said extensions for transfer of data from said parallel registers to said serial registers in two groups.