Divisor transform type high-speed electronic division system

Claim 2

An electronic division system comprising means for transforming an input divisor signal into a given number of integers, said given number being a number selected on a basis of a desired accuracy index, means for separately multiplying each of said given number of transformed divisor signals by a dividend signal to produce said given number of multiplication products, and means comprising said given number of adders for adding at least some of the products of said multiplication to produce a quotient signal which is equal to a quotient of said dividend divided by said divisor.

Claim 3

The division system of claim 1 and means of separating said multiplication product signals into high and low subproduct signals, means for shifting said products so that a high subproduct signals from one multiplication product is added in said adding means to a low subproduct signal from another multiplication product.

Claim 4

The division system of claim 2 and means for discarding at least one of said subproduct signals at the least significant end of said quotient signal, said discarded signals being determined by the given number which is selected as an accuracy index.

Claim 5

The division system of any one of the claims 1-3 wherein said transforming means comprises read-only memories, there being a separate read-only memory means for each of said given number of integers.

Claim 6

The division system of claim 4 and means for simultaneously applying said divisor signal to all of said read-only memory means.

Claim 7

The division system of claim 5 and means for selecting between said read-only memory means.

Claim 8

The division system of claim 4 wherein each of said given number of multiplication products is an integer signal sent in parallel over a plurality of wires, said wires being divided into high and low groups of wires, and means for connecting a high group of wires carrying one of said integers to one of said adders and a low group of wires carrying the same one of said integers to another of said adders.

Claim 9

The division system of claim 7 and means for interconnecting said adders in cascade to transfer signals between them which cause said adders to align their output signals according to the needs of said quotient signals.

Claim 10

The division system of claim 4 wherein there are a plurality of said multiplying means, said plurality being equal to said given number, and means for connecting an output from each of said transforming means to an input of an individually associated one of said separate multiplying means.

Claim 11

The division system of claim 4 wherein there is one of said multiplying means, and clock means for sequentially enabling said multiplying means to sequentially make said separate multiplications of each of said transformed divisor signals by said dividend signals.

Claim 12

The division system of claim 10 and demultiplex means responsive to said clock means for applying subproducts of said separate multiplications to said adders for adding said multiplication products in a sequence corresponding to said quotient.

Claim 13

The division system of claim 11 and means for interconnecting said adders in cascade to transfer signals between them which cause said adders to align their output signals according to the needs of said quotient signals.

Claim 14

An electronic division network for dividing a dividened by a divisor to produce a quotient having an accuracy fixed by an accuracy index, said accuracy index being determined by a selected one (N) of a plurality of numbers, a plurality equal to N of read-only memory means having a common input carrying signals representing said divisor, said divisor being an address signal for each of said memory means, each of said read-only memory means storing a predetermined substring of digits at each divisor signal address signal which can appear at said common input, a plurality equal to N of multiplication means having a common input carrying a signal representing said dividend, each of said multiplication means being individually associated with a corresponding one of said read-only memories, whereby each of said N multiplication means concurrently receives a corresponding one of said substring of digits and a dividend appearing at the common input of said multiplication means, means responsive to a multiplication product from each of said multiplication means for producing 2 N subproduct of strings of digits, a plurality equal to N of adding means connected in cascade for adding said subproducts to produce a quotient signal, a signal on said cascade connection shifting said additions to produce a quotient, and means for inserting a decimal point between the outputs of preselected ones of said adding means.

Claim 15

An electronic division network for dividing a dividened by a divisor to produce a quotient having an accuracy fixed by an accuracy index, said accuracy index being determined by a selected one (N) of a plurality of numbers, a plurality equal to N of read-only memory means having a common input carrying signals representing said divisor, said divisor being an address signal for each of said memory means, each of said read-only memory means storing a predetermined substring of digits at each divisor signal address signal which can appear at said common input, a plurality equal to N of multiplication means having a common input carrying a signal representing said dividend, each of said multiplication means being individually associated with a corresponding one of said read-only memories, whereby each of said N multiplication means concurrently receives a corresponding one of said substring of digits and a dividend appearing at the common input of said multiplication means, means responsive to a multiplication product from each of said multiplication means for producing 2 N subproduct of strings of digits, a plurality equal to N of adding means connected in cascade for adding said subproducts to produce a quotient signal, a signal on said cascade connection shifting said additions to produce a quotient, and means for inserting a decimal point between the outputs of preselected ones of said adding means.

Claim 16

The network of claim 13 wherein said dividend and divisor are expressed in terms of h-bit length binary words, each of said multiplication means being an h-by-h-bit multiplier.

Claim 17

The network of claim 14 and means for selectively eliminating at least one of said subproduct strings responsive to said accuracy index.

Claim 18

An electronic division network for dividing a dividend by a divisor to produce a quotient having an accuracy fixed by an accuracy index, said accuracy index being determined by a selected one (N) of a plurality of numbers, N read-only memory means having a common input for receiving signals representing said divisor, address signals of said memory means being expressed in terms of said divisor signals, each of said read-only memory means storing a predetermined subtransform of part of said divisor at each address signal which can appear at said common input, multiplier means having an input for receiving signals representing said dividend, clock means for successively applying each part of said transformed divisor to said multiplier means whereby said multiplier means successively receives strings of digits selected from said read-only memory means responsive to said divisor signals, said multiplier means successively multiplying each successive string by a dividend signal appearing at the input of said multiplier means, means responsive to said successive multiplication products from each of said successive multiplications for producing 2 N subproduct strings of digits, a plurality of adding means having carry terminals connected in cascade, demultiplexer means for applying each of the 2 N subproducts to selected ones of said adding means for adding said subproducts with digital shifts signalled at said carry terminals to produce a quotient signal.

Claim 19

An electronic division network for dividing a dividend by a divisor to produce a quotient having an accuracy fixed by an accuracy index, said accuracy index being determined by a selected one (N) of a plurality of numbers, N read-only memory means having a common input for receiving signals representing said divisor, address signals of said memory means being expressed in terms of said divisor signals, each of said read-only memory means storing a predetermined subtransform of part of said divisor at each address signal which can appear at said common input, multiplier means having an input for receiving signals representing said dividend, clock means for successively applying each part of said transformed divisor to said multiplier means whereby said multiplier means successively receives strings of digits selected from said read-only memory means responsive to said divisor signals, said multiplier means successively multiplying each successive string by a dividend signal appearing at the input of said multiplier means, means responsive to said successive multiplication products from each of said successive multiplications for producing 2 N subproduct strings of digits, a plurality of adding means having carry terminals connected in cascade, demultiplexer means for applying each of the 2 N subproducts to selected ones of said adding means for adding said subproducts with digital shifts signalled at said carry terminals to produce a quotient signal.

Claim 20

The network of claim 16 and means for inserting a decimal point between the outputs of preselected ones of said adding means.