US4373168A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital time-base corrector having a wide correction range
Assignee: NEC Corp
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Filing: 1980-03-28
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Granted: 1983-02-08
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Expires: 2000-03-28
Abstract
Abstract Disclosed is a digital time-base corrector (TBC) capable of correcting not only time-base fluctuation (jitter) but also a time-base change contained in a VTR-reproduced television video signal which experiences large changes in the horizontal scanning period during, for example, special-motion reproduction. The leading edge of a horizontal sync pulse is delayed by a variable delay means, and gate pulse is produced from the delayed leading edge and non-delayed trailing edge of the sync pulse. The delay time is controlled in response to the pulse width of the gate pulse. A burst gate pulse is produced from the trailing edge of the gate pulse. The burst gate pulse gates the video signal to extract a color burst, which is used to produce a clock pulse. The video signal is converted into a digital signal and stored in a digital memory in response to the clock pulse.
Inventors
- 👤 Mineo Mizukami
- 👤 Tatsuo Konishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:52
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/896
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
337 words
A time-base corrector for correcting the time-base error contained in a television video signal comprising: (a) means for generating a first clock pulse in synchronism with said television video signal; (b) means responsive to said first clock pulse for converting said television video signal to a digital video signal; (c) digital memory means for storing said digital video signal; (d) means responsive to said first clock pulse, a first horizontal sync signal and a first vertical sync signal contained in said television video signal for generating write-in address data designating an address at which said digital video signal is to be written into said digital memory; (e) means for generating a second clock pulse in synchronism with a reference signal; (f) means responsive to a second horizontal sync signal and a second vertical sync signal contained in said reference signal and said second clock pulse for generating read-out address data designating an address at which the stored digital video signal is read out from said digital memory; and (g) means responsive to said second clock pulse for converting the read-out digital video signal to an analog signal; wherein said first clock pulse generating means comprises: (i) delay means for delaying the leading edge of said first horizontal sync signal to generate a delayed leading edge signal; (ii) means for generating a first gate pulse of a predetermined pulse width in response to said delayed leading edge signal; (iii) means for gating said first horizontal sync signal with said first gate pulse to extract a trailing edge signal from said first horizontal sync signal; (iv) means for controlling the delay time of said delay means in response to the time interval between said delayed leading edge signal and said trailing edge signal; (v) means for generating a second gate pulse in response to said trailing edge signal; and (vi) means for gating said television video signal with said second gate pulse to extract a color burst signal; said first color pulse being produced from said color burst signal.
Claim 2
Dependent Claim
337 words
A time-base corrector for correcting the time-base error contained in a television video signal comprising: (a) means for generating a first clock pulse in synchronism with said television video signal; (b) means responsive to said first clock pulse for converting said television video signal to a digital video signal; (c) digital memory means for storing said digital video signal; (d) means responsive to said first clock pulse, a first horizontal sync signal and a first vertical sync signal contained in said television video signal for generating write-in address data designating an address at which said digital video signal is to be written into said digital memory; (e) means for generating a second clock pulse in synchronism with a reference signal; (f) means responsive to a second horizontal sync signal and a second vertical sync signal contained in said reference signal and said second clock pulse for generating read-out address data designating an address at which the stored digital video signal is read out from said digital memory; and (g) means responsive to said second clock pulse for converting the read-out digital video signal to an analog signal; wherein said first clock pulse generating means comprises: (i) delay means for delaying the leading edge of said first horizontal sync signal to generate a delayed leading edge signal; (ii) means for generating a first gate pulse of a predetermined pulse width in response to said delayed leading edge signal; (iii) means for gating said first horizontal sync signal with said first gate pulse to extract a trailing edge signal from said first horizontal sync signal; (iv) means for controlling the delay time of said delay means in response to the time interval between said delayed leading edge signal and said trailing edge signal; (v) means for generating a second gate pulse in response to said trailing edge signal; and (vi) means for gating said television video signal with said second gate pulse to extract a color burst signal; said first color pulse being produced from said color burst signal.
Claim 3
Dependent Claim
36 words
A time-base corrector in accordance with claim 1, wherein the pulse width of said second gate pulse is controlled in response to said time interval between said delayed leading edge signal and said trailing edge signal.
Claim 4
Dependent Claim
149 words
A time-base corrector in accordance with claim 1, wherein said write-in address data generating means comprises, a voltage controlled oscillator, first means for comparing the phase difference between said second gate pulse and an output signal from said voltage controlled oscillator, means responsive to said first comparing means for generating a first phase error signal, means for delaying said second gate pulse by an interval of time equal to one horizontal scanning period of said television video signal to produce a delayed second gate pulse, second means for comparing the phase difference between said second gate pulse and said delayed second gate pulse, means responsive to said second comparing means for generating a second phase error signal, means for mixing said first phase error signal with said second phase error signal to produce an oscillator control signal and for applying said oscillator control signal to said voltage controlled oscillator.
Claim 5
Dependent Claim
32 words
A time-base corrector in accordance with claim 3, wherein said television video signal gating means includes delay means for delaying said second gate pulse in response to said second phase error signal.
Claim 6
Dependent Claim
133 words
A time-base corrector in accordance with claim 3, wherein said write-in address data generating means further comprises, means for counting an output signal from said voltage controlled oscillator, means responsive to said first vertical sync signal for storing the binary state of said counter, first means for comparing the binary state of said counter with the binary state of said storing means and for generating a first control signal when said counter binary state and said storing means binary state are coincident, second means for comparing the binary state and of said counter with a fixed binary state for generating a second control signal when said counter binary state exceeds said fixed binary state, and means responsive to the simultaneous presence of said first and second control signals for resetting said counting means.
Claim 7
Dependent Claim
103 words
A time-base corrector in accordance with claim 5, wherein said write-in address data generating means further comprises a write-in vertical address counter for generating write-in vertical address data and a latch circuit for storing said write-in vertical address data in response to at least one of said first vertical sync signal and the simultaneous presence of said first and second control signals, said read-out address data generating means further comprising a read-out vertical address counter for generating read-out vertical address data, said read-out vertical address counter being reset to the contents in said latch circuit in response to said second vertical sync signal.
Claim 8
Dependent Claim
25 words
A time-base corrector in accordance with claim 3, wherein said voltage controlled oscillator and said second gate pulse delaying means are composed of monostable multivibrators.
Claim 9
Dependent Claim
25 words
A time-base corrector in accordance with claim 7, wherein said voltage controlled oscillator and said second gate pulse delaying means are composed of monostable multivibrators.
Claim 10
Dependent Claim
18 words
A time-base corrector in accordance with claim 8, wherein said monostable multivibrators are formed on a single chip.
References Cited (Backward Citations)
US4216504A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-02-07 | 1986-08-09 | 1987-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-02-07 | 1990-08-09 | 1991-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-02-07 | 1994-08-09 | 1995-02-08 | $7700.00 | Window Closed / Lapsed |