Hybrid unlatching flip-flop logic element

Claim 2

A superconductive circuit comprising first and second Josephson junction latching gates (J 1 , J 2 ) each having V=0 and V≠0 states, a critical current which when exceeded causes the gate to switch from its V=0 to its V≠0 state, and a drop-back level below which the gate switches from its V≠0 to its V=0 state, electrode means (N 1 , N 2 ) for applying DC bias current (I b ) to said gates, control means (I c1 , I c2 ) for selectively switching said gates from their V=0 to their V≠0 states, one of said gates being initially set to its V=0 state and the other to its V≠0 state, CHARACTERIZED IN THAT said circuit is rendered unlatching by a passive network (1, 3, 4, 5) coupling said gates to one another and responsive to the switching of states of said one gate from its V=0 to its V≠0 state for applying a transient current to said other gate in a direction opposite to the direction said bias current flows therein and effective to reduce current in said other gate below the drop-back level thereof, thereby automatically resetting said other gate from its V≠0 to its V=0 state.

Claim 3

The circuit of claim 1 wherein the bias current flowing in each of said gates, when in its V=0 state, is less than the critical current of said gate.

Claim 4

The circuit of claim 1 wherein said passive network is responsive to the switching of either of said gates for generating a transient current which is effective to reverse the sign of the current on the other of said gates, and wherein the duration of said transient current is long enough to discharge the capacitance of said other gate to at least zero voltage.

Claim 5

The circuit of claim 1, 2 or 3 wherein said electrode means includes a first node (N 1 ) for applying bias current to said gates and a second node (N 2 ) for extracting bias current from said gates, said passive network comprises a first resistor (R 1 ) connected between said first node (N 1 ) and a common third node (N 3 ), a second resistor (R 2 ) connected between said second node (N 2 ) and said common node (N 3 ), and inductance means (L 3 ) connected between a fourth node (N 4 ) and said common node (N 3 ), and wherein said first gate (J 1 ) is connected between said first and fourth nodes and said second gate (J 2 ) is connected between said second and fourth nodes.

Claim 6

The circuit of claim 4 wherein the following relationships are satisified: the smaller of L 3 /R 1 and L 3 /R 2 is greater than the largest of (L 1 +L 2 )/(R 1 +R 2 ), (R 1 +R 2 )C 1 and (R 1 +R 2 )C 2 , and ##EQU2## where R J is the resistance of a gate; C is the capacitance of a gate; and 2Δ is the superconductor energy gap voltage; so that the switching of said first gate reverses the sign of the current through said second gate, and conversely.

Claim 7

The circuit of claim 5 wherein said inductance means (L 3 ) is included in a circuit branch which forms an output line of said circuit.

Claim 8

The circuit of claim 6 wherein said resistors R 1 and R 2 and said common node N 3 therebetween form a resistive divider between said nodes N 1 and N 2 , and including a plurality of said dividers connected in parallel between said nodes N 1 and N 2 , and wherein said inductance means (L 3 ) comprises a plurality of fanout lines each including inductance means (L' 3 ) connected between said fourth node (N 4 ) and separate ones of the common nodes (N 3 ).

Claim 9

The circuit of claim 6 wherein said fanout line includes a plurality of parallel resistors, each forming a separate fanout line, connected in series between said nodes N 3 and N 4 .

Claim 10

The circuit of claims 1, 2, or 3 including first and second coupled loop circuits, said first loop circuit having a first node (N 1 ) for receiving bias current, said second loop circuit having a second node (N 2 ) for extracting bias current, said first loop circuit comprising a first circuit branch in which said first gate is located, a first resistor (R 1 ), said inductance means (I 3 ) and first inductance means (L 1 ) connected in series with one another, said second loop circuit comprising a second circuit branch in which said second gate is located, a second resistor (R 2 ), said inductance means (L 3 ), and second inductance means (L 2 ) connected in series with one another, where said first and second inductance means (L 1 and L 2 ) correspond to the self-inductance of said first and second circuit branches, respectively, and said passive network comprises said first and second resistors (R 1 and R 2 ) and said inductance means (L 3 ).

Claim 11

The circuit of claim 9 wherein the smaller of L 3 /R 1 and L 3 /R 2 is greater than the largest of (R 1 +R 2 )C 1 , (R 1 +R 2 )C 2 and (L 1 +L 2 )/(R 1 +R 2 ).

Claim 12

The circuit of claim 9 wherein said inductance means (L 3 ) comprises separate inductors forming a transformer having a mutual inductance (M) and self-inductances (L 5 and L 6 ).

Claim 13

The circuit of claim 11 wherein M, L 5 and L 6 are approximately equal.

Claim 14

The circuit of claim 1 comprising a first loop circuit including a first circuit branch in which said first gate is located, a first resistor (R 1 ), and first inductance means (L 1 ) connected in series with one another, a second loop circuit including a second circuit branch in which said second gate is located, a second resistor (R 2 ), and second inductance means (L 2 ) connected in series with one another, where said first and second inductance means (L 1 and L 2 ) correspond respectively to the self-inductance of said first and second circuit branches, said bias current is applied to a first node (N 1 ) of said first loop and is extracted from a second node (N 2 ) of said second loop, and said passive network comprises an impedance element Z 4 coupling said first and second nodes.

Claim 15

The circuit of claim 13 wherein said impedance element comprises a capacitor.

Claim 16

The circuit of claim 13 wherein said impedance element comprises a resistor.

Claim 17

A superconductive circuit including first, second, and third inductance means (L 1 , L 2 , L 3 , respectively), a first loop circuit comprising a first circuit branch, a first Josephson junction gate (J 1 ) located in said first branch, a first resistor (R 1 ), said third inductance means (L 3 ), and said first inductance means (L 1 ) connected in series with one another, a second loop circuit comprising a second circuit branch, a second Josephson junction gate (J 2 ) located in said second branch, a second resistor (R 2 ), said third inductance means (L 3 ), and said second inductance means (L 2 ) connected in series with one another, where said first and second inductance means (L 1 and L 2 ) correspond respectively to the self-inductance of said first and second circuit branches, respectively, and said third inductance means (L 3 ) forms a common circuit branch between said loop circuits, said first loop circuit including a first node (N 1 ) adapted to receive DC bias current (I b ), said second loop circuit including a second node (N 2 ) adapted to extract said DC bias current, and control means (I c1 , I c2 ) for selectively switching said gates from their V=0 to their V≠0 states, said circuit satisfying the following inequalities: the smaller of L 3 /R 1 and L 3 /R 2 is greater than the largest of (R 1 +R 2 )C 1 , (R 1 +R 2 )C 2 and (L 1 +L 2 )/(R 1 +R 2 ), and ##EQU3## where R J is the resistance of a gate; C is the capacitance of a gate; and 2Δ is the superconductor energy gap voltage; so that the switching of said first gate reverses the sign of the current through said second gate, and conversely.

Claim 18

A superconductive circuit including first, second, and third inductance means (L 1 , L 2 , L 3 , respectively), a first loop circuit comprising a first circuit branch, a first Josephson junction gate (J 1 ) located in said first branch, a first resistor (R 1 ), said third inductance means (L 3 ), and said first inductance means (L 1 ) connected in series with one another, a second loop circuit comprising a second circuit branch, a second Josephson junction gate (J 2 ) located in said second branch, a second resistor (R 2 ), said third inductance means (L 3 ), and said second inductance means (L 2 ) connected in series with one another, where said first and second inductance means (L 1 and L 2 ) correspond respectively to the self-inductance of said first and second circuit branches, respectively, and said third inductance means (L 3 ) forms a common circuit branch between said loop circuits, said first loop circuit including a first node (N 1 ) adapted to receive DC bias current (I b ), said second loop circuit including a second node (N 2 ) adapted to extract said DC bias current, and control means (I c1 , I c2 ) for selectively switching said gates from their V=0 to their V≠0 states, said circuit satisfying the following inequalities: the smaller of L 3 /R 1 and L 3 /R 2 is greater than the largest of (R 1 +R 2 )C 1 , (R 1 +R 2 )C 2 and (L 1 +L 2 )/(R 1 +R 2 ), and ##EQU3## where R J is the resistance of a gate; C is the capacitance of a gate; and 2Δ is the superconductor energy gap voltage; so that the switching of said first gate reverses the sign of the current through said second gate, and conversely.

Claim 19

A superconductive circuit comprising a first loop circuit including a first Josephson junction gate (J 1 ), a self-inductance (L 1 ) associated with said first gate, and a first resistor (R 1 ) connected in series with one another, a first node (N 1 ) for applying DC bias current (I b ) to said first loop circuit, and a third node (N 3 ) for extracting current from said first loop circuit, a second loop circuit comprising a second Josephson junction gate (J 2 ), a self-inductance (L 2 ) associated with said second gate, and a second resistor (R 2 ) connected in series with one another, a second node (N 2 ) for extracting said bias current from said second loop circuit, and a fourth node (N 4 ) for applying bias current to said second loop circuit, each of said gates having a current drop-back level below which the gate switches from its V≠0 state, to its V=0 state, an impedance element (Z 4 ) coupling said first and second nodes (N 1 , N 2 ) so that the switching of said first gate (J 1 ) applies a current transient to said second gate (J 2 ) effective to reduce the current thereof below its drop-back level, and conversely, and means connecting said third and fourth nodes to one another.

Claim 20

A superconductive circuit comprising a first loop circuit including a first Josephson junction gate (J 1 ), a self-inductance (L 1 ) associated with said first gate, and a first resistor (R 1 ) connected in series with one another, a first node (N 1 ) for applying DC bias current (I b ) to said first loop circuit, and a third node (N 3 ) for extracting current from said first loop circuit, a second loop circuit comprising a second Josephson junction gate (J 2 ), a self-inductance (L 2 ) associated with said second gate, and a second resistor (R 2 ) connected in series with one another, a second node (N 2 ) for extracting said bias current from said second loop circuit, and a fourth node (N 4 ) for applying bias current to said second loop circuit, each of said gates having a current drop-back level below which the gate switches from its V≠0 state, to its V=0 state, an impedance element (Z 4 ) coupling said first and second nodes (N 1 , N 2 ) so that the switching of said first gate (J 1 ) applies a current transient to said second gate (J 2 ) effective to reduce the current thereof below its drop-back level, and conversely, and means connecting said third and fourth nodes to one another.