Skewed matrix address generator

Claim 2

In an address generator for an M-interleaved memory for accessing at the memory system's maximum access rate successive elements of either a row or a column of a matrix stored in a skewed matrix pattern, apparatus for generating the sequences of appropriate memory addresses for the desired row or column, comprising: a base register having an input connected to a first adder which adds an input value A to the contents in the base register so that the output of the adder can be stored and subsequently used as a pointer to the beginning of the current row in the matrix in memory being accessed; an index register having an input connected to a second added for adding an input value B to the contents of the index register and that sum being conditionally added in a third adder to an input value C which sum is then stored in the index register so that it can be subsequently used as a pointer to the column element in the matrix in memory being accessed; a fourth adder having inputs connected to the base register and the index register for generating from the row and column pointers the actual memory address of the next matrix element to be accessed; whereby in response to a series of clock pulses a sequence of memory addresses needed to access the desired row or column will be generated with the result appearing in natural order.

Claim 3

In a vector processing system including a vector processor having an instruction unit and an execution unit responsive to instructions generated by the instruction unit to execute vector operations and a data bus connecting an M-interleaved memory to the execution unit, an address generator for the M-interleaved memory for accessing at the memory system's maximum access rate successive elements of either a row or a column of a matrix stored in a skewed matrix pattern, the address generator generating the sequences of appropriate memory addresses for the desired row or column, comprising: a first adder having a first input connected to said instruction unit; a base register having an input connected to the output of said first adder which adds a value A at said first input thereof to the contents in the base register, so that the output of said first adder can be stored and subsequently used as a pointer to the beginning of the current row in the matrix in memory being accessed; a second adder having a first input connected to said instruction unit; a third adder having a first input connected to said instruction unit; an index register having an input connected to said second adder which adds a value B at said first input thereof to the contents of the index register, that sum being conditionally added by said third adder to an input value C at said first input thereof, which sum is then stored in said the index register, for indicating which column element in the matrix is to be accessed; a fourth adder having inputs connected to the base register and the index register and an output connected to the address input of said memory for generating from the row and column pointers the actual memory address of the next matrix element to be accessed; a decoder connected between said instruction unit and said address generator for decoding instructions generated by said instruction unit into said values A, B, and C; whereby in response to a series of clock pulses, a sequence of memory addresses needed to access the desired row or column will be generated with the result appearing in natural order.

Claim 4

In a vector processing system including a vector processor having an instruction unit and an execution unit responsive to instructions generated by the instruction unit to execute vector operations and a data bus connecting an M-interleaved memory to the execution unit, an address generator for the M-interleaved memory for accessing at the memory system's maximum access rate successive elements of either a row or a column of a matrix stored in a skewed matrix pattern, the address generator generating the sequences of appropriate memory addresses for the desired row or column, comprising: a first adder having a first input connected to said instruction unit; a base register having an input connected to the output of said first adder which adds a value A at said first input thereof to the contents in the base register, so that the output of said first adder can be stored and subsequently used as a pointer to the beginning of the current row in the matrix in memory being accessed; a second adder having a first input connected to said instruction unit; a third adder having a first input connected to said instruction unit; an index register having an input connected to said second adder which adds a value B at said first input thereof to the contents of the index register, that sum being conditionally added by said third adder to an input value C at said first input thereof, which sum is then stored in said the index register, for indicating which column element in the matrix is to be accessed; a fourth adder having inputs connected to the base register and the index register and an output connected to the address input of said memory for generating from the row and column pointers the actual memory address of the next matrix element to be accessed; a decoder connected between said instruction unit and said address generator for decoding instructions generated by said instruction unit into said values A, B, and C; whereby in response to a series of clock pulses, a sequence of memory addresses needed to access the desired row or column will be generated with the result appearing in natural order.