Method of and circuit arrangement for automatic signal-level control

Claim 3

A method as defined in claim 1, comprising the further step of setting an upper and a lower limit for the dynamic range of the modified magnitude of the incoming signal between steps (a) and (b).

Claim 4

A method as defined in claim 1 or 2 wherein the modified magnitude of the incoming signal is periodically sampled between steps (a) and (b).

Claim 5

A method as defined in claim 3 wherein the updated modifier produced in step (d) is delayed by substantially a sampling period before being used to multiply another sample of the incoming signal in a repeat of step (a).

Claim 6

A circuit arrangement for controlling the level of an incoming signal, comprising: first multiplier means with inputs connected to one lead carrying the incoming signal and to another lead carrying a level-controlling modification signal for producing a modified signal amplitude on a further lead; a first adder with inputs respectively connected to receive the modified signal amplitude from said further lead and a reference signal of fixed magnitude for differentially combining same to produce an error signal; second multiplier means with inputs connected to said first adder and to said other lead for producing a corrective signal as the product of said modification signal times said error signal times a fractional coefficient; a second adder with inputs respectively connected to said second multiplier means and to said other lead for algebraically combining said modification signal with said corrective signal to produce an updated modification signal; delay means connecting an output of said second adder to said other lead for delivering the updated modification signal thereto; and signal-receiving means connected to at least one of said other and further leads.

Claim 7

A circuit arrangement for controlling the level of an incoming signal, comprising: first multiplier means with inputs connected to one lead carrying the incoming signal and to another lead carrying a level-controlling modification signal for producing a modified signal amplitude on a further lead; a first adder with inputs respectively connected to receive the modified signal amplitude from said further lead and a reference signal of fixed magnitude for differentially combining same to produce an error signal; second multiplier means with inputs connected to said first adder and to said other lead for producing a corrective signal as the product of said modification signal times said error signal times a fractional coefficient; a second adder with inputs respectively connected to said second multiplier means and to said other lead for algebraically combining said modification signal with said corrective signal to produce an updated modification signal; delay means connecting an output of said second adder to said other lead for delivering the updated modification signal thereto; and signal-receiving means connected to at least one of said other and further leads.

Claim 8

A circuit arrangement as defined in claim 5, further comprising saturation means between said first multiplier means and said further lead for setting an upper and a lower limit for the dynamic range of said modified signal amplitude.

Claim 9

A circuit arrangement as defined in claim 5 or 6, further comprising periodically operating sampling means inserted between said first multiplier means and said first adder for feeding said modified signal amplitude to the latter at discrete intervals.

Claim 10

A circuit arrangement as defined in claim 7 wherein said delay means introduces a lag substantially corresponding to an operating cycle of said sampling means.