Integratable single pulse circuit

Claim 1

A circuit for generating a single pulse in response to an applied trigger having a width greater than the generated single pulse comprising: an input port for receiving an applied input trigger; an output port coupled to said input port for providing a single pulse having a select width in response to said input trigger, said output port comprising a first transistor having its base coupled to said input port and its collector uncoupled for connection to an external connection; timing means coupled to said input port for delaying said input trigger by a select time t, said timing means comprising (a) a second and a third transistor, said second transistor having its base coupled to said input port and its collector coupled to a first temperature compensated capacitor and to the base of said third transistor, and said third transistor having a collector coupled to a second temperature compensated capacitor and to said shunt means, and (b) two temperature compensated current sources having a fifth transistor having its collector coupled to said second transistor collector and its emitter coupled to a first resistor, a sixth transistor having its collector coupled to said third transistor collector and its emitter coupled to a second resistor, a first diode means coupled to an input of a second diode means, and a rail current source coupled to the output of said second diode means and to the base of said fifth transistor and to the base of said sixth transistor, thereby said timing means is independent of temperature; and shunt means coupled to said output port for truncating said input trigger in response to said input trigger delayed by t applied thereto to provide said single pulse, said shunt means comprising a fourth transistor having its base coupled to the collector of said third transistor and its collector coupled to the base of said first transistor.