Method and apparatus for encoding digital data

Claim 3

The method of claim 1 wherein said first reference point substantially coincides with the middle portion of a bit cell interval.

Claim 4

The method of claim 1 wherein said second reference point substantially coincides with the trailing edge of a bit cell interval.

Claim 5

The method of claim 1 wherein said step of producing a respective second transition after sensing every n successive binary bits of said first value comprises producing a said second transition after every 2 binary bits if the total number of successive binary bits of said first value is an even number; and if the total number of successive binary bits of said first value is an odd number greater than 3, producing a said second transition after every 2 binary bits and a said second transition after the final 3 binary bits are sensed.

Claim 6

The method of claim 4 wherein, if the total number of binary bits of said first value is greater than 3, then the minimum separation between succeeding transitions is no less than 1.5 bit cell intervals, and the separation between remaining succeeding transitions is substantially equal to 2 bit cell intervals and for an odd number of successive binary bits the separation between the final two transitions is substantially equal to 3 bit cell intervals.

Claim 7

The method of claim 1 wherein said step of producing a respective second transition after sensing every n successive binary bits of said first value comprises determining if the total number of said successive binary bits is odd or even and, if odd and greater than 3, producing a said second transition after sensing the first 3 successive binary bits and thereafter producing a said second transition after sensing each 2 successive binary bits, and if the total number of said successive binary bits is even and greater than 3, producing a said second transition after sensing each 2 successive binary bits.

Claim 8

The method of claim 1 wherein said step of producing a respective second transition after sensing every n successive binary bits of said first value comprises producing said second transition at the trailing edge of the last bit cell of said successive binary bits if the total number of said successive binary bits is less than 4.

Claim 9

The method of claim 1 wherein said step of producing a respective second transition after sensing every m successive binary bits of said second value comprises producing a said second transition following the production of a first transition after 3 successive binary bits have been sensed if the total number of said successive binary bits is greater than 3.

Claim 10

The method of claim 8 wherein said step of producing a respective second transition after sensing every m successive binary bits of said second value further comprises producing additional second transitions after each 4 successive binary bits, following the first 3 successive binary bits, have been sensed.

Claim 11

The method of claim 1 wherein said step of producing a respective second transition after sensing m successive binary bits of said second value comprises producing a first of said second transitions after 3 successive binary bits have been sensed and succeeding ones of said second transitions after every 4 successive binary bits have been sensed thereafter, provided that said successive binary bits of said second value are preceded by a single binary bit of said first value.

Claim 12

The method of claim 10, further comprising the step of inhibiting the production of a second transition after 4 successive binary bits have been sensed if said last mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.

Claim 13

The method of claim 1 wherein m=4 if said successive binary bits of said second value are preceded by at least two successive binary bits of said first value.

Claim 14

The method of claim 12 further comprising the step of inhibiting the production of a second transition after 4 successive binary bits have been sensed if said last-mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.

Claim 17

The method of claim 14 comprising the step of inhibiting the production of a second transition if said last-mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.

Claim 18

Apparatus for encoding an input digital data formed of binary bits of first and second values occupying consecutive bit cells of predetermined intervals, comprising: first transition generating means for producing a first transition at a first reference point in a bit cell when a binary bit of said second value changes over to a binary bit of said first value; sensing means for sensing successive binary bits of said first value and for sensing successive binary bits of said second value; and second transition generating means for producing a respective second transition at a second reference point in a bit cell after said sensing means senses every n successive binary bits of said first value (n=2 or 3); said second transition generating means further producing a respective second transition at said second reference point in a bit cell when said sensing means senses at least two successive binary bits of said first value and also after sensing every m successive binary bits of said second value (m=3 or 4), such that said last-mentioned second transition at said second reference point is separated from a said first transition by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of said second transitions are separated from each other by no more than 4 bit cell intervals.

Claim 19

Apparatus for encoding an input digital data formed of binary bits of first and second values occupying consecutive bit cells of predetermined intervals, comprising: first transition generating means for producing a first transition at a first reference point in a bit cell when a binary bit of said second value changes over to a binary bit of said first value; sensing means for sensing successive binary bits of said first value and for sensing successive binary bits of said second value; and second transition generating means for producing a respective second transition at a second reference point in a bit cell after said sensing means senses every n successive binary bits of said first value (n=2 or 3); said second transition generating means further producing a respective second transition at said second reference point in a bit cell when said sensing means senses at least two successive binary bits of said first value and also after sensing every m successive binary bits of said second value (m=3 or 4), such that said last-mentioned second transition at said second reference point is separated from a said first transition by at least 1.5 bit cell intervals but no more than 4.5 bit cell intervals and successive ones of said second transitions are separated from each other by no more than 4 bit cell intervals.

Claim 20

The apparatus of claim 16 wherein said first reference point coincides with the middle portion of a bit cell interval.

Claim 21

The apparatus of claim 16 wherein said second reference point substantially coincides with the trailing edge of a bit cell interval.

Claim 22

The apparatus of claim 16 wherein said second transition generating means comprises means for producing a said second transition after every 2 binary bits of said first value if the total number of successive binary bits of said first value is an even number; means for determining when the total number of successive binary bits of said first value is an odd number greater than 3, and means for producing a said second transition after every 2 binary bits and a said second transition after said sensing means senses the first 3 binary bits.

Claim 23

The apparatus of claim 16 wherein said second transition generating means comprises means for determining if the total number of said successive binary bits of said first value is odd or even; means for producing a said second transition after sensing the first 3 successive binary bits and thereafter producing a said second transition after sensing each 2 successive binary bits if said total number of said successive binary bits is odd and greater than 3; and means for producing a said second transition after sensing each 2 successive binary bits if said total number of said successive binary bits is even and greater than 3.

Claim 24

The apparatus of claim 16 wherein said second transition generating means comprises means for producing said second transition at the trailing edge of the last bit cell of said successive binary bits of said first value if the total number of successive binary bits is less than 4.

Claim 25

The apparatus of claim 16 wherein said second transition generating means comprises means for producing a said second transition following the production of a first transition after 3 successive binary bits of said second value have been sensed if the total number of said successive binary bits is greater than 3.

Claim 26

The apparatus of claim 22 wherein said second transition generating means further comprises means for producing additional second transitions after each 4 successive binary bits, following the first 3 successive binary bits, have been sensed.

Claim 27

The apparatus of claim 16 wherein said second transition generating means comprises means for producing a first of said second transitions after 3 successive binary bits of said second value have been sensed, and means for producing succeeding ones of said second transitions after every 4 successive binary bits have been sensed thereafter, provided that said sensing means senses that said successive binary bits of said second value are preceded by a single binary bit of said first value.

Claim 28

The apparatus of claim 24, further comprising inhibit means for inhibiting the production of a second transition after 4 successive binary bits have been sensed if said last mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.

Claim 29

Apparatus for encoding input digital data formed of binary bits of first and second values occupying consecutive bit cells of predetermined intervals, comprising: first transition generating means for producing a first transition at a first reference point in a bit cell occupied by a binary bit of said first value when a binary bit of said second value changes over to said binary bit of said first value; sensing means for sensing successive binary bits of said first value and for sensing successive binary bits of said second value; second transition generating means for producing a second transition at a second reference point in the bit cell occupied by the last of said successive binary bits of said first value, and for producing a respective second transition at a second reference point in a bit cell after said sensing means senses every 2 successive binary bits of said first value; detecting means for detecting if the total number of said successive binary bits of said first value is an odd number in excess of 3, means for dividing the last 5 of said successive binary bits into respective groups of 2 and 3 binary bits if said total number is an odd number in excess of 3 such that said producing means produces a said second transition at a said second reference point between said groups; and said second transition generating means produces a respective second transition at said second reference point in a bit cell when at least two successive binary bits of said first value are followed by a binary bit of said second value and also after said sensing means senses every 3 successive bits of said second value, such that said last-mentioned second transition is separated from a said first transition by at least 1.5 bit cell intervals and is separated from the next-following second transition by no more than 3 bit cell intervals.

Claim 30

Apparatus for encoding input digital data formed of binary bits of first and second values occupying consecutive bit cells of predetermined intervals, comprising: first transition generating means for producing a first transition at a first reference point in a bit cell occupied by a binary bit of said first value when a binary bit of said second value changes over to said binary bit of said first value; sensing means for sensing successive binary bits of said first value and for sensing successive binary bits of said second value; second transition generating means for producing a second transition at a second reference point in the bit cell occupied by the last of said successive binary bits of said first value, and for producing a respective second transition at a second reference point in a bit cell after said sensing means senses every 2 successive binary bits of said first value; detecting means for detecting if the total number of said successive binary bits of said first value is an odd number in excess of 3, means for dividing the last 5 of said successive binary bits into respective groups of 2 and 3 binary bits if said total number is an odd number in excess of 3 such that said producing means produces a said second transition at a said second reference point between said groups; and said second transition generating means produces a respective second transition at said second reference point in a bit cell when at least two successive binary bits of said first value are followed by a binary bit of said second value and also after said sensing means senses every 3 successive bits of said second value, such that said last-mentioned second transition is separated from a said first transition by at least 1.5 bit cell intervals and is separated from the next-following second transition by no more than 3 bit cell intervals.

Claim 31

The apparatus of claim 26 further comprising inhibit means for inhibiting the production of a second transition if said last-mentioned second transition would be separated from any other transition by less than 1.5 bit cell intervals.