Address retrieval in an electronic dictionary and language interpreter

Claim 1

A word translation or dictionary device comprising: input means actuated to enter character information representative of a desired word in a first language; decoder means responsive to the input means for developing an initial address code corresponding to character information designating at least a leading character of the word entered by the input means; first memory means containing a plurality of words in said language stored in a plurality of separate groups, the words in each of said groups having the leading same character and being stored in coded locations correlated to said address code of said leading character; second memory means containing address code information representing the location of a translated word in a second language equivalent to the desired word stored in the first memory means; address means provided for synchronously addressing the first memory means and the second memory means so that the desired word is retrieved from the first memory means together with the retrieval of the translated word generated from the second memory means; comparison means responsive to the input means and words retrieved by said address means from the first memory means for determining equivalency between the word entered by the input means and the word retrieved from the first memory means; said address means being responsive to the decoder means for directly accessing a selected one of said separate groups stored in the first memory means defined by the leading character address code thereof and responsive to comparison results determined by the comparison means for causing further access of code information related to the specific location of said desired word in said group until said equivalency is obtained; and display means responsive to said equivalency determined by the comparision means for indicating the translated word designated by the code information generated from the second memory means.

Claim 4

The device according to claims 1 or 2, wherein the address means comprises an address counter for causing access of the code information stored in the first and the second memory means according to the contents therein, and an adder circuit actuated during said further access in response to comparison results, for adding one to the contents stored in the address counter, said address codes for the words in each of said groups being consecutive numbers separated in value by said one.