US4366471A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable speed digital reproduction system using a digital low-pass filter
Assignee: Victor Company of Japan Ltd
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Filing: 1981-02-20
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Granted: 1982-12-28
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Expires: 2001-02-20
Abstract
Abstract A variable speed reproduction system includes a memory in which analog signal is stored as sampled digital data. A variable frequency digital low-pass filter is receptive of the data read out of the memory. A counter provides a binary representation of a count value of time base clock pulses to a comparator for detecting a coincidence with a variable speed setting of a variable resistor. The output of the comparator resets the counter and is used as a source of reading the data out of the memory. The cut-off frequency of the digital filter is controlled in response to the setting of the resistor so that the high frequency component of the analog equivalent of the input digital data which is higher than one-half of the data reading frequency is eliminated to prevent foldover distortion noise which might occur as a result of the difference between the recording and reproducing speeds. The data read out of the memory is fed to a digital-to-analog converter at a constant frequency and the quantum noise of the output data is filtered out by an analog low-pass filter.
Inventors
- 👤 Masao Kasuga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:44
CPC Classifications
G; G11; G11B; G11B27/00; G11B27/005
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
218 words
A system for reproducing an analog signal which is stored as sampled data in memory means at a variable speed which may differ from the speed at which the analog signal is sampled and recorded into said memory means, comprising: a clock source for generating clock pulses occurring at a frequency substantially corresponding to the speed at which said sampled data is recorded into said memory means; a binary counter for counting said clock pulses to generate a first binary output representing the count value of said clock pulses; means for generating a second binary output representing said variable speed; means for detecting a match between said first and second binary outputs to reset said binary counter to an initial count value and reading the stored data out of said memory means in response to the occurrence of the detected match; a digital low-pass filter for eliminating a high frequency component of the analog equivalent of the sampled data, the cut-off frequency of said filter being variable in response to the value of said second binary output so that the cut-off frequency corresponds substantially to one-half of the frequency at which said detected match occurs; and a digital-to-analog converter for converting a filtered signal from said digital low-pass filter at a constant frequency into a corresponding analog signal.
Claim 2
Independent Claim
218 words
A system for reproducing an analog signal which is stored as sampled data in memory means at a variable speed which may differ from the speed at which the analog signal is sampled and recorded into said memory means, comprising: a clock source for generating clock pulses occurring at a frequency substantially corresponding to the speed at which said sampled data is recorded into said memory means; a binary counter for counting said clock pulses to generate a first binary output representing the count value of said clock pulses; means for generating a second binary output representing said variable speed; means for detecting a match between said first and second binary outputs to reset said binary counter to an initial count value and reading the stored data out of said memory means in response to the occurrence of the detected match; a digital low-pass filter for eliminating a high frequency component of the analog equivalent of the sampled data, the cut-off frequency of said filter being variable in response to the value of said second binary output so that the cut-off frequency corresponds substantially to one-half of the frequency at which said detected match occurs; and a digital-to-analog converter for converting a filtered signal from said digital low-pass filter at a constant frequency into a corresponding analog signal.
Claim 3
Dependent Claim
26 words
A system as claimed in claim 1, wherein said constant frequency at which said analog signal is converted corresponds to the frequency of said clock source.
Claim 4
Dependent Claim
21 words
A system as claimed in claim 1, further comprising an analog low-pass filter connected to the output of said digital-to-analog converter.
Claim 5
Dependent Claim
36 words
A system as claimed in claim 1, 2 or 3, wherein said digital low-pass filter is receptive of the sampled data read out of said memory means at the frequency at which said detected match occurs.
Claim 6
Dependent Claim
106 words
A system as claimed in claim 1, 2 or 3, wherein said memory means comprises a first memory into which said sampled data are written at the frequency of said clock source and a second memory, further comprising means for reading the stored data out of said first memory into said digital low-pass filter at the frequency of said clock source and writing the output of said digital low-pass filter into said second memory at the frequency of said clock source, and means for reading the stored data out of said second memory at the frequency at which said detected match occurs into said digital-to-analog converter.
Claim 7
Dependent Claim
68 words
A system as claimed in claim 1, 2 or 3, wherein said means for generating said second binary output comprises a manually adjustable variable resistor connected between terminals of a voltage source, an analog-to-digital converter for converting a voltage developed at a wiper tap point of said variable resistor into a corresponding digital signal, and a latch for storing said digital signal in response to said detected match.
Claim 8
Dependent Claim
47 words
A system as claimed in claim 6, further comprising a differentiator for differentiating the voltage developed at said wiper tap point of said variable resistor and means for combining the voltage developed at said wiper tap point with said differentiated voltage for application to said analog-to-digital converter.
Claim 9
Dependent Claim
77 words
A system as claimed in claim 6, further comprising a a second manually adjustable variable resistor connected between terminals of a voltage source, a differentiator for differentiating a voltage developed at a wiper tap point of said second variable resistor and means for combining the voltage developed at the wiper tap point of said second variable resistor with the voltage developed at the wiper tap point of the first-mentioned variable resistor for application to said analog-to-digital converter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-27 | 1986-06-28 | 1986-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-27 | 1990-06-28 | 1990-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-27 | 1994-06-28 | 1994-12-28 | $7700.00 | Window Closed / Lapsed |