US4364081A
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Method and apparatus for processing a digital color video signal
Assignee: Sony Corp
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Filing: 1981-04-16
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Granted: 1982-12-14
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Expires: 2001-04-16
Abstract
Abstract A method for processing a digital color video signal formed of 8-bit words, includes the recording steps of converting each 8-bit word into a 10-bit word in accordance with a predetermined mapping function, grouping the 10-bit words into 48 word blocks, adding to each block an identification signal, identification signal check words P 1 and Q 1 , and data check words P 2 and Q 2 , the latter being formed by the equations: ##EQU1## where T -1 , T -2 , . . . T - (n-1), T -n , T 1 , T 2 , . . . T n-1 , T n are distinct, non-zero elements of a Galois field (2 m ); and includes the reproducing steps of reconverting each of the 10-bit words to its corresponding 8-bit word in accordance with the predetermined mapping function with the reconverted 8-bit words forming a data unit for each 12 words thereof and a data block for each 48 words thereof, detecting whether any of the 8-bit words contain an error by failing to satisfy the mapping function reconversion, determining that each data unit that includes an 8-bit word having an error is erroneous, detecting and correcting any errors in the identification signals by means of the identification signal check words P 1 and Q 1 , determining whether each erroneous data block and data unit is capable of being corrected and concealing each erroneous data unit that is determined to be uncorrectable and correcting errors in the 8-bit words in each erroneous data block and data unit that is determined to be correctable, by means of the data check words P 2 and Q 2 and parity words, respectively, thereby forming a continuous, composite digital color video signal, and correcting the phase of the color sub-carrier of each data unit of the composite digital color video signal by comparison of a reference signal with the identification signal of the block to which each respective data unit belongs.
Inventors
- 👤 Yoshitaka Hashimoto
- 👤 Norihisa Shirota
- 👤 Kaichi Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:38
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1806; G11B20/1813
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
114 words
A method of processing a digital signal comprised of a plurality of N-bit words which have been code converted from a plurality of M-bit words in accordance with a predetermined mapping function, said method comprising the steps of: reconverting each of said N-bit words to a respective one of said M-bit words in accordance with said mapping function, with said plurality of reconverted M-bit words forming a data unit for every predetermined number of words thereof; detecting whether any of said M-bit words contain an error by failing to satisfy the mapping function during said step of reconverting; and determining that each data unit that includes an M-bit word having an error is erroneous.
Claim 2
Independent Claim
114 words
A method of processing a digital signal comprised of a plurality of N-bit words which have been code converted from a plurality of M-bit words in accordance with a predetermined mapping function, said method comprising the steps of: reconverting each of said N-bit words to a respective one of said M-bit words in accordance with said mapping function, with said plurality of reconverted M-bit words forming a data unit for every predetermined number of words thereof; detecting whether any of said M-bit words contain an error by failing to satisfy the mapping function during said step of reconverting; and determining that each data unit that includes an M-bit word having an error is erroneous.
Claim 3
Dependent Claim
27 words
A method according to claim 1; in which the number of bits in each N-bit word is greater than the number of bits in each M-bit word.
Claim 4
Dependent Claim
33 words
A method according to claim 2; in which the number of bits in each N-bit word is equal to 10 and the number of bits in each M-bit word is equal to 8.
Claim 5
Dependent Claim
36 words
A method according to claim 1; further comprising the step of determining whether each erroneous data unit is capable of being corrected, based on the number of M-bit words containing an error in each data unit.
Claim 6
Dependent Claim
28 words
A method according to claim 4; further comprising the step of concealing each erroneous data unit that is determined to be uncorrectable by substituting another data unit therefor.
Claim 7
Dependent Claim
57 words
A method according to claim 5; in which said digital signal is a digital video signal comprised of successive field intervals, each field interval having a plurality of data units, and each said another data unit is substituted from the field interval next previous to the respective field interval including the erroneous data unit to be concealed.
Claim 8
Dependent Claim
49 words
A method according to claim 4; in which at least one error correcting word is added to said reconverted digital signal every predetermined number of M-bit words, and further comprising the step of correcting errors in said M-bit words by means of said at least one error correcting word.
Claim 9
Dependent Claim
58 words
A method according to claim 7; in which two error correcting words are added to each predetermined number of data units of M-bit words, and said step of correcting corrects the error in each M-bit word by means of at least one of the error correcting words associated with the data unit to which the erroneous word belongs.
Claim 10
Independent Claim
63 words
A method of processing a digital signal comprising the steps of: sampling an analog signal at a predetermined frequency; converting the sampled signal into digitized form; forming a data block for every predetermined number of bits of said digital signal; adding an identification signal to each data block for identification thereof; and adding an error correcting signal to each of said identification signals.
Claim 11
Independent Claim
63 words
A method of processing a digital signal comprising the steps of: sampling an analog signal at a predetermined frequency; converting the sampled signal into digitized form; forming a data block for every predetermined number of bits of said digital signal; adding an identification signal to each data block for identification thereof; and adding an error correcting signal to each of said identification signals.
Claim 12
Dependent Claim
39 words
A method according to claim 9; further comprising the steps of detecting whether each said identification signal includes an error, and correcting any error detected in each identification signal by means of the respective error correcting signal added thereto.
Claim 13
Dependent Claim
163 words
A method according to claim 10; in which said digital signal is a digital color video signal having a luminance component and a chrominance component with a color sub-carrier, further comprising the steps of dividing each data block into a plurality of data units, adding the identification signal from each data block to each of the data units included therein, detecting whether any errors exist in each data unit, determining whether errors detected in each data unit are capable of being corrected, concealing errors in each data unit that are determined to be uncorrectable by substituting an associated data unit therefor, said associated data unit having an identification signal from its corresponding data block added thereto, comparing the identification signal from each concealed and unconcealed data unit with a reference identification signal, and inverting the phase of the color sub-carrier in a data unit when its added identification signal does not satisfy a predetermined compared relation with respect to said reference identification signal.
Claim 14
Independent Claim
91 words
A method of processing a digital signal comprising the steps of: sampling an analog signal at a predetermined frequency; converting said sampled signal into digitized form; forming a data word every m bits; and adding two check words P and Q to every n data words, each check word having m bits and said check words being formed by the equations: ##EQU10## where T -1 , T -2 ,-T - (n-1),T -n ,T 1 ,T 2 ,-,T n-1 ,T n are distinct, non-zero elements of a Galois field (2 m ).
Claim 15
Independent Claim
91 words
A method of processing a digital signal comprising the steps of: sampling an analog signal at a predetermined frequency; converting said sampled signal into digitized form; forming a data word every m bits; and adding two check words P and Q to every n data words, each check word having m bits and said check words being formed by the equations: ##EQU10## where T -1 , T -2 ,-T - (n-1),T -n ,T 1 ,T 2 ,-,T n-1 ,T n are distinct, non-zero elements of a Galois field (2 m ).
Claim 16
Dependent Claim
120 words
Apparatus for processing a digital signal comprised of a plurality of N-bit words which have been code converted from a plurality of M-bit words in accordance with a predetermined mapping function, comprising: reconverting means for reconverting each of said N-bit words to a respective one of said M-bit words in accordance with said mapping function, with said plurality of reconverted M-bit words forming a data unit for every predetermined number of words thereof; first detecting means for detecting whether any of said M-bit words contain an error by failing to satisfy the mapping function when reconverted by said reconverting means; and first judging means for determining that each data unit that includes an M-bit word having an error is erroneous.
Claim 17
Dependent Claim
120 words
Apparatus for processing a digital signal comprised of a plurality of N-bit words which have been code converted from a plurality of M-bit words in accordance with a predetermined mapping function, comprising: reconverting means for reconverting each of said N-bit words to a respective one of said M-bit words in accordance with said mapping function, with said plurality of reconverted M-bit words forming a data unit for every predetermined number of words thereof; first detecting means for detecting whether any of said M-bit words contain an error by failing to satisfy the mapping function when reconverted by said reconverting means; and first judging means for determining that each data unit that includes an M-bit word having an error is erroneous.
Claim 18
Dependent Claim
26 words
Apparatus according to claim 13; in which the number of bits in each N-bit word is greater than the number of bits in each M-bit word.
Claim 19
Dependent Claim
31 words
Apparatus according to claim 14; in which the number of bits in each N-bit word is equal to 10 and the number of bits in each M-bit is equal to 8.
Claim 20
Dependent Claim
36 words
Apparatus according to claim 13; further comprising second judging means for determining whether each erroneous data unit is capable of being corrected, based on the number of M-bit words containing an error in each data unit.
Claim 21
Dependent Claim
27 words
Apparatus according to claim 16; further comprising concealing means for concealing each erroneous data unit that is determined to be uncorrectable by substituting another data unit therefor.
Claim 22
Dependent Claim
56 words
Apparatus according to claim 17; in which said digital signal is a digital video signal comprised of successive field intervals, each field interval having a plurality of data units, and each said another data unit is substituted from the field interval next previous to the respective field interval including the erroneous data unit to be concealed.
Claim 23
Dependent Claim
48 words
Apparatus according to claim 16; in which at least one error correcting word is added to said reconverted digital signal every predetermined number of M-bit words, and further comprising correcting means for correcting errors in said M-bit words by means of said at least one error correcting word.
Claim 24
Dependent Claim
56 words
Apparatus according to claim 19; in which two error correcting words are added to each predetermined number of data units of M-bit words, and said correcting means corrects the error in each M-bit word by means of at least one of the error correcting words associated with the data unit to which the erroneous word belongs.
Claim 25
Dependent Claim
76 words
Apparatus for processing a digital signal, comprising: sampling means for sampling an analog signal at a predetermined frequency; converting means for converting the sampled signal into digitized form; forming means for forming a data block for every predetermined number of bits of said digital signal; first adding means for adding an identification signal to each data block for identification thereof; and second adding means for adding an error correcting signal to each of said identification signals.
Claim 26
Dependent Claim
76 words
Apparatus for processing a digital signal, comprising: sampling means for sampling an analog signal at a predetermined frequency; converting means for converting the sampled signal into digitized form; forming means for forming a data block for every predetermined number of bits of said digital signal; first adding means for adding an identification signal to each data block for identification thereof; and second adding means for adding an error correcting signal to each of said identification signals.
Claim 27
Dependent Claim
60 words
Apparatus according to claim 21; further comprising receiving means for receiving the digital signal having said identification and correcting signals added thereto, said receiving means including detecting means for detecting whether each said identification signal includes an error, and correcting means for correcting any error detected in each identification signal by means of the respective error correcting signal added thereto.
Claim 28
Dependent Claim
186 words
Apparatus according to claim 22; in which said digital signal is a digital color video signal having a luminance component and a chrominance component with a color sub-carrier, said receiving means further including dividing means for dividing each data block into a plurality of data units, third adding means for adding the identification signal from each data block to each of the data units included therein, second detecting means for detecting whether any errors exist in each data unit, judging means for determining whether errors detected in each data unit are capable of being corrected, concealing means for concealing errors in each data unit that are determined to be uncorrectable by substituting an associated data unit therefor, said associated data unit having an identification signal from its corresponding data block added thereto, comparing means for comparing the identification signal from each concealed and unconcealed data unit with a reference identification signal, and phase inverting means for inverting the phase of the color sub-carrier in a data unit when its added identification signal does not satisfy a predetermined compared relation with respect to said reference identification signal.
Claim 29
Dependent Claim
97 words
Apparatus for processing a digital signal, comprising: sampling means for sampling an analog signal at a predetermined frequency; converting means for converting said sampled signal into digitized form; forming means for forming a data word every m bits; and adding means for adding two check words P and Q to every n data words, each check word having m bits and said check words being formed by the equations: ##EQU11## where T -1 ,T -2 ,-T - (n-1),T -n ,T 1 ,T 2 ,-,T n-1 ,T.sup.n are distinct, non-zero elements of a Galois field (2 m ).
Claim 30
Dependent Claim
97 words
Apparatus for processing a digital signal, comprising: sampling means for sampling an analog signal at a predetermined frequency; converting means for converting said sampled signal into digitized form; forming means for forming a data word every m bits; and adding means for adding two check words P and Q to every n data words, each check word having m bits and said check words being formed by the equations: ##EQU11## where T -1 ,T -2 ,-T - (n-1),T -n ,T 1 ,T 2 ,-,T n-1 ,T.sup.n are distinct, non-zero elements of a Galois field (2 m ).
Claim 31
Dependent Claim
34 words
Apparatus according to claim 24; further comprising first and second check word generating means for generating said two check words P and Q as a function of predetermined first and second generator polynomials, respectively.
Claim 32
Dependent Claim
74 words
Apparatus according to claim 25; in which each of said first and second check word generating means includes first latch means serially receiving said data words and producing an output, second latch means producing an output, and operational means for operating on the outputs of said first and second latch means in accordance with the respective one of said first and second generator polynomials and for supplying an output to said second latch means.
Claim 33
Dependent Claim
53 words
Apparatus according to claim 24; further comprising receiving means for receiving said digital signal having said check words P and Q added thereto, said receiving means including detecting means for detecting any errors in said received data words, and correcting means for correcting at least some errors detected in said received data words.
Claim 34
Dependent Claim
164 words
Apparatus according to claim 27; in which said correcting means includes first syndrome generator means for generating a first syndrome in response to each first check word P and its associated n data words, second syndrome generator means for generating a second syndrome in response to each second check word Q and its associated n data words, first syndrome operating means for operating on said first syndrome in accordance with a predetermined function and for producing an output in response thereto, second syndrome operating means for operating on said second syndrome in accordance with a predetermined function and for producing an output in response thereto, comparator means for comparing the outputs of said first and second syndrome operating means to detect whether an error is present in each data word and for producing an output in response thereto, and an error correcting circuit for correcting errors in said data words when said comparator means indicates that an error is present in a data word.
Claim 35
Dependent Claim
89 words
Apparatus according to claim 28; in which said correcting means further includes comparator control means for determining whether every n data words contain at least one error and whether each said at least one error is capable of being corrected and for inhibiting the operation of said comparator means when it is determined that no errors are present in a group of n data words or when it is determined that said at least one error in a group of n data words is not capable of being corrected.
Claim 36
Dependent Claim
126 words
Apparatus according to claim 29; in which said correcting means further includes memory means for storing each n data words, and multiplexer means for selecting as an output the output of said memory means or the output of said error correcting circuit in response to said comparator means so that the output of said memory means is selected when no errors are present in a group of n data words or when at least one error is present in a group of n data words and is determined to be not capable of correction, and the output of said error correcting means is selected when at least one error is present in a group of n data words and is determined to be capable of correction.
Claim 37
Dependent Claim
161 words
Apparatus according to claim 29; further including counter means for counting the number of errors present in each group of n data words and for producing a counted output in response thereto, and said comparator control means includes first syndrome comparator means for detecting whether the output of said first syndrome operating means is a logic level "0" signal and for producing an output in response thereto, second syndrome comparator means for detecting whether the output of said second syndrome operating means is a logic level "0" signal and for producing an output in response thereto, and gate means for producing a comparator inhibit signal in response to the outputs of said first and second syndrome comparator means and said counted output for inhibiting the operation of said comparator means when no errors are present in a group of n data words or when at least one error in a group of n data words is not capable of being corrected.
References Cited (Backward Citations)
US4081826A
Cited
US4106053A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-13 | 1986-06-14 | 1986-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-13 | 1990-06-14 | 1990-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-13 | 1994-06-14 | 1994-12-14 | $7700.00 | Window Closed / Lapsed |