Method of and circuit arrangement for determining the magnitude of an unknown resistance element

Claim 3

An analog/digital converter for digitally determining the magnitude R i of an unknown resistance element, comprising: a one-shot pulse generator, provided with a first timing network, iteratively triggerable to establish a recurrent gating period T; a free-running pulse generator, provided with a second timing network, for emitting a train of counting pulses with a recurrence period t<<T; switchover means in said first timing network having a first, a second and a third position for respectively connecting a first known calibrating resistance of magnitude R 1 , a second known calibrating resistance of magnitude R 2 =mR 1 with m>1, and said unknown resistance element in circuit with a fixed capacitor; counting means connected to be stepped by said free-running pulse generator in an active state of said one-shot pulse generator for registering a pulse count N 1 during one gating period with said switchover means in said first position, a pulse count N 2 during another gating period with said switchover means in said second position, and a pulse count N i during a further gating period with said switchover means in said third position; and arithmetic means connected to said counting means for calculating the ratio R i /R 1 from the counts N 1 , N 2 , N i , said counts N 1 , N 2 , N i varying substantially in direct proportion to the magnitudes R 1 , R 2 , R i , and from the factor m, said arithmetic means being adapted to calculate said ratio according to the formula ##EQU10##

Claim 4

An analog/digital converter for digitally determining the magnitude R i of an unknown resistance element, comprising: a one-shot pulse generator, provided with a first timing network, iteratively triggerable to establish a recurrent gating period T; a free-running pulse generator, provided with a second timing network, for emitting a train of counting pulses with a recurrence period t<<T; switchover means in said first timing network having a first, a second and a third position for respectively connecting a first known calibrating resistance of magnitude R 1 , a second known calibrating resistance of magnitude R 2 =mR 1 with m>1, and said unknown resistance element in circuit with a fixed capacitor; counting means connected to be stepped by said free-running pulse generator in an active state of said one-shot pulse generator for registering a pulse count N 1 during one gating period with said switchover means in said first position, a pulse count N 2 during another gating period with said switchover means in said second position, and a pulse count N i during a further gating period with said switchover means in said third position; and arithmetic means connected to said counting means for calculating the ratio R i /R 1 from the counts N 1 , N 2 , N i , said counts N 1 , N 2 , N i varying substantially in direct proportion to the magnitudes R 1 , R 2 , R i , and from the factor m, said arithmetic means being adapted to calculate said ratio according to the formula ##EQU10##

Claim 5

A converter as defined in claim 2 wherein said second timing network comprises a fixed resistor in circuit with another fixed capacitor, said one-shot pulse generator further including a coincidence gate with inputs connected to the capacitors of both timing networks and with an output connected to said counting means, said second timing network forming a resistive feedback path between the output and one of the inputs of said coincidence gate for temporarily blocking same upon a charging of the capacitor of said second timing network.

Claim 6

A converter as defined in claim 3 wherein said second timing network, said coincidence gate, said counting means and said arithmetic means are part of a microprocessor also including signaling means for triggering said one-shot pulse generator and operating said switchover means in a predetermined sequence.