US4360841A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data correction circuit
Assignee: Sony Corp
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Filing: 1980-12-24
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Granted: 1982-11-23
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Expires: 2000-12-24
Abstract
Abstract A time code correction circuit is formed of an input circuit for receiving an input time code; first and second memories for storing data representing the time code; an adder for selectively incrementing or decrementing data to be supplied to the first and second memories; a comparator comparing the data stored in the first memory with the input time code; a switch controlled by the comparator for selectively supplying the adder with the input time code and the data started second memory; and an output circuit coupled to provide the contents of the second memory as a corrected output time code. Where the time code is reproduced from a time code track recorded on a magnetic tape, the correction circuit is favorably adapted to produce a continuous time code sequence despite dropout in the recorded time code. Also, if a jump occurs in the recorded time code sequence, the correction circuit causes the output time code to reflect such jump with a minimum of signal disturbance.
Inventors
- 👤 Michio Mita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:39
CPC Classifications
G; G11; G11B; G11B27/00; G11B27/02; G11B27/022; G11B27/024; G11B20/00; G11B20/10; G11B20/18; G11B27/10; G11B27/102; G11B27/107; G11B27/19; G11B27/28; G11B27/32; G11B27/322; G11B27/323; G11B2220/00; G11B2220/90
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
129 words
A data correction circuit for correcting errors in a sequence of generally regularly and progressively incremented input data comprising input circuit means for receiving the input data; first memory means for storing data; second memory means for storing data; incrementing means for incrementing data supplied thereto in a selected one of positive and negative senses and supplying the incremented data therefrom to said first and said second memory means; comparing means for comparing the data stored in said first memory means with said input data; switch means controlled by said comparing means for selectively supplying said incrementing means with one of said input data and the data stored in said second memory means; and output means coupled to at least said second memory means for providing corrected output data.
Claim 2
Dependent Claim
129 words
A data correction circuit for correcting errors in a sequence of generally regularly and progressively incremented input data comprising input circuit means for receiving the input data; first memory means for storing data; second memory means for storing data; incrementing means for incrementing data supplied thereto in a selected one of positive and negative senses and supplying the incremented data therefrom to said first and said second memory means; comparing means for comparing the data stored in said first memory means with said input data; switch means controlled by said comparing means for selectively supplying said incrementing means with one of said input data and the data stored in said second memory means; and output means coupled to at least said second memory means for providing corrected output data.
Claim 3
Dependent Claim
27 words
A data correction circuit according to claim 1, wherein said input circuit means includes a reading transducer for reproducing time code data recorded on a record medium.
Claim 4
Dependent Claim
61 words
A data correction circuit according to claim 1, wherein said comparing means includes means to detect whether the sequence of input data is being progressively incremented in the positive sense or is being progressively incremented in the negative sense, and to control said incrementing means to increment the data supplied thereto in the respective one of the positive and negative senses.
Claim 5
Dependent Claim
29 words
A data correction circuit according to claim 1, wherein said comparing means provides first and second memory control signals, at staggered times, to said first and second memory means.
Claim 6
Dependent Claim
116 words
A data correction circuit according to claim 4, wherein when said comparing means determines that said input data and the data stored in said first memory means are equal, the input data is supplied to said incrementing means so that the incremented input data is stored in both said first and said second memory means, but when said comparing means determines that said input data and the data stored in said first memory means are unequal, the data stored in said second memory means is supplied to said incrementing means at least during the occurrence of the second memory control signal, so that the data in said second memory means is incremented and again stored therein.
Claim 7
Dependent Claim
54 words
A data correction circuit according to claim 1, wherein said output means includes a switch having an output to provide the output data, inputs respectively coupled to receive the contents of said first and said second memory means, and a control terminal; and an error switch providing a control signal to said control terminal.
References Cited (Backward Citations)
US4134131A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-22 | 1986-05-24 | 1986-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-22 | 1990-05-24 | 1990-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-22 | 1994-05-24 | 1994-11-23 | $7700.00 | Window Closed / Lapsed |