Multi-sampling-channel pulse compressor

Claim 2

A low-sidelobe pulse compression processor for reducing the processing loss in echo signals caused by sampling time error and for improving range resolution comprising: means for receiving an echo return signal from an energy transmission and generating I and Q baseband signals from said echo signal; a first signal processing channel comprising first sampling means for sampling said I and Q signals in accordance with pulses from a first clock signal having a predetermined sampling frequency; first means for compressing said sampled I and Q signals from said first sampling means; first means for generating the signal envelope for said compressed I and Q signals from said first compressing means; a second signal processing channel comprising second sampling means for sampling said I and Q signals with pulses from a second clock signal having said predetermined sampling frequency but with the second clock signal pulses interlaced, in time, approximated midway between the pulses of said first clock signal second means for compressing said sampled I and Q signals from said second sampling means; second means for generating the signal envelope for said compressed I and Q signals from said second compressing means; and multiplying means for multiplying the output envelope signals from said first and second envelope generating means to obtain a low-sidelobe narrow output signal.

Claim 3

A low-sidelobe pulse compression processor as defined in claim 1, wherein said first and second envelope generating means each comprise a circuit for generating the magnitude of the respective sampled I and Q signals applied thereto.

Claim 4

A low-sidelobe pulse compression processor as defined in claim 1, wherein said first and second envelope generating means each comprise: means for squaring said compressed I and Q signals; means for adding the squared I and Q signals from said squaring means; and means for generating a signal representative of the square root of the output signal from said adding means.

Claim 5

A low-sidelobe pulse compression processor as defined in claim 3, wherein said first and second compressing means each comprise: an analog-to-digital converter for converting said sampled I and Q signals into digital form; and a digital compression circuit for digitally compressing said digitized I and Q signals.

Claim 6

A low-sidelobe pulse compression processor as defined in claim 3, wherein said first and second sampling means include means for generating said first and second clock signals at the Nyquist sampling frequency for the I and Q baseband signals.

Claim 7

A low-sidelobe pulse compression method for reducing the processing loss in echo signals caused by sampling time errors in pulse compression processing circuitry comprising the steps of: receiving an echo signal from an energy transmission; generating I and Q baseband signals from said echo signal; sampling said I and Q signals in accordance with pulses from a first clock signal having a predetermined sampling frequency and also sampling said I and Q signals in accordance with pulses from a second clock signal having said predetermined sampling frequency but with said second clock signal pulses interlaced, in time, approximately midway between the pulses of said first clock signal; compressing said first-clock-sampled I and Q signals and also compressing said second-clock-sampled I and Q signals; generating a first signal envelope from said compressed first-clock-sampled I and Q signals and a second signal envelope from said compressed second-clock-sampled I and Q signals; and multiplying said generated first and second signal envelopes together to obtain a low-sidelobe narrow output signal.

Claim 8

A low-sidelobe pulse compression method for reducing the processing loss in echo signals caused by sampling time errors in pulse compression processing circuitry comprising the steps of: receiving an echo signal from an energy transmission; generating I and Q baseband signals from said echo signal; sampling said I and Q signals in accordance with pulses from a first clock signal having a predetermined sampling frequency and also sampling said I and Q signals in accordance with pulses from a second clock signal having said predetermined sampling frequency but with said second clock signal pulses interlaced, in time, approximately midway between the pulses of said first clock signal; compressing said first-clock-sampled I and Q signals and also compressing said second-clock-sampled I and Q signals; generating a first signal envelope from said compressed first-clock-sampled I and Q signals and a second signal envelope from said compressed second-clock-sampled I and Q signals; and multiplying said generated first and second signal envelopes together to obtain a low-sidelobe narrow output signal.

Claim 9

A low-sidelobe pulse compression method as defined in claim 6, wherein said signal envelope generating step comprises the step of generating the magnitude of said compressed I and Q signals sampled in accordance with said first clock signal and the magnitude of said compressed I and Q signals sampled in accordance with said second clock signal.

Claim 10

A low-sidelobe pulse compression method as defined in claim 6, wherein said signal envelope generating step comprises the steps of: squaring said compressed first-clock-sampled I signals and Q signals and squaring said compressed second-clock-sampled I and Q signals; adding said squared first-clock-sampled I and Q compressed signals together and adding said squared second-clock-sampled I and Q compressed signals together; and generating a signal representative of the square root of the sum of said squared first-clock-sampled I and Q signals and the square root of the sum of said squared second-clock-sampled I and Q signals.

Claim 11

A low-sidelobe pulse compression processor as defined in claim 6, wherein said sampling step comprises the step of sampling said I and Q signals in accordance with pulses from a first clock signal at the Nyquist sampling frequency and also sampling said I and Q signals in accordance with pulses from a second clock signal at the Nyquist sampling frequency, but with said second clock signal interlaced, in time, approximately midway between the pulses of said first clock signal.

Claim 12

A low-sidelobe pulse compression processor for reducing the processing loss in echo signals caused by sampling time errors and for improving range resolution comprising: means for receiving an echo signal from an energy transmission and generating I and Q baseband signals from said echo signal; n signal processing channels, where n is an integer >2, wherein said first signal processing channel comprises: first sampling means for sampling said I and Q signals in accordance with pulses from a first clock signal having a predetermined sampling frequency; first means for compressing said I and Q signals from first sampling means; first means for generating the signal envelope for said compressed I and Q signals from said first compressing means; and wherein said i th signal processing channel, where 1≦i≦n, comprises: i th sampling means for sampling said I and Q signals in accordance with pulses from an i th clock signal having said predetermined sampling frequency but with said i th clock pulses interlaced, in time, with said first clock signal pulses such that said i th clock signal pulses are (i) (360°)/(n) out of phase with said first clock pulses; i th means for compressing said i th clock sampled I and Q signals from said i th sampling means; i th means for generating the signal envelope for said compressed I and Q signals from said i th compressing means; and multiplying means for multiplying together the output envelope signals generated in each of said n signal processing channels to obtain a low-sidelobe narrow output signal.

Claim 13

A low-sidelobe pulse compression processor for reducing the processing loss in echo signals caused by sampling time errors and for improving range resolution comprising: means for receiving an echo signal from an energy transmission and generating I and Q baseband signals from said echo signal; n signal processing channels, where n is an integer >2, wherein said first signal processing channel comprises: first sampling means for sampling said I and Q signals in accordance with pulses from a first clock signal having a predetermined sampling frequency; first means for compressing said I and Q signals from first sampling means; first means for generating the signal envelope for said compressed I and Q signals from said first compressing means; and wherein said i th signal processing channel, where 1≦i≦n, comprises: i th sampling means for sampling said I and Q signals in accordance with pulses from an i th clock signal having said predetermined sampling frequency but with said i th clock pulses interlaced, in time, with said first clock signal pulses such that said i th clock signal pulses are (i) (360°)/(n) out of phase with said first clock pulses; i th means for compressing said i th clock sampled I and Q signals from said i th sampling means; i th means for generating the signal envelope for said compressed I and Q signals from said i th compressing means; and multiplying means for multiplying together the output envelope signals generated in each of said n signal processing channels to obtain a low-sidelobe narrow output signal.

Claim 14

A low-sidelobe pulse compression processor as defined in claim 10, wherein said n envelope generating means each comprise a circuit for generating the magnitude of the respective sampled I and Q signals applied thereto.

Claim 15

A low-sidelobe pulse compression processor as defined in claim 10, wherein said n envelope generating means each comprise: means for squaring said compressed I and Q signals; means for adding the squared I and Q signals from said squaring means; and means for generating a signal representative of the square root of the signal output of said adding means.

Claim 16

A low-sidelobe pulse compression processor as defined in claim 10, wherein each of said sampling means in said n signal processing channels comprises means for generating a clock signal at a predetermined sampling frequency equal to the system information bandwidth.