US4357549A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic frequency alteration circuit
Assignee: National Security Agency
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Filing: 1980-12-02
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Granted: 1982-11-02
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Expires: 2000-12-02
Abstract
Abstract An apparatus for altering frequencies such that any one of a plurality of input frequencies automatically becomes another specified frequency. The value of the output frequency will remain constant regardless of which input frequency chosen, as long as the input frequencies have the relationship a, 2a, 4a, 8a . . . An input signal is received by a descending cascade of units composed of multipliers and filters. The multiplier portion of each unit must be in series with and receive the input stimuli before the filter portion of each unit. Each multiplier portion of the unit must also have a control input of a predetermined value. A phase lock loop inside of a feedback loop compensates for instantaneous variations of frequency in the input signal. This feedback loop is connected from the multiplier-filter unit to the control input for each multiplier portion.
Inventors
- 👤 Kelly A. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:21
CPC Classifications
H; H03; H03B; H03B21/00; H03B21/01; H03B21/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
148 words
An electrical circuit, comprising: an input to which is applied one of a plurality of input signals; means for providing a plurality of control signals; a plurality of first order units, each including (1) multiplier means connected to said input and one of said control signals for generating first order intermediate signals equal to the albegraic sum and difference of said input signal and a selected one of said control signals and (2) filter means for passing a selected one of said first order intermediate signals; and at least one second order unit including (1) multiplier means connected to said plurality of first order units for generating second order intermediate signals equal to the algebraic sum and difference of said selected first order intermediate signal and a selected one of said control signals and (2) filter means for passing a selected one of said second order intermediate signals.
Claim 2
Dependent Claim
148 words
An electrical circuit, comprising: an input to which is applied one of a plurality of input signals; means for providing a plurality of control signals; a plurality of first order units, each including (1) multiplier means connected to said input and one of said control signals for generating first order intermediate signals equal to the albegraic sum and difference of said input signal and a selected one of said control signals and (2) filter means for passing a selected one of said first order intermediate signals; and at least one second order unit including (1) multiplier means connected to said plurality of first order units for generating second order intermediate signals equal to the algebraic sum and difference of said selected first order intermediate signal and a selected one of said control signals and (2) filter means for passing a selected one of said second order intermediate signals.
Claim 3
Dependent Claim
43 words
The circuit of claim 1 wherein the input signals have the frequency relationship a×2 0 , a×2 1 , . . . , a×2 n-1 , where n is the total number of input signals and a is the lowest frequency input signal.
Claim 4
Dependent Claim
28 words
The circuit of claim 2, wherein the number of first order units is n/2 where n is an even number, and (n-1)/2+1 when n is an odd number.
Claim 5
Dependent Claim
12 words
The circuit of claim 1 wherein said filter means are band-pass filters.
Claim 6
Dependent Claim
55 words
The circuit of claim 1 further comprising an output and wherein said at least one second order unit further includes a plurality of second and higher order units connected in descending cascade order with the filter means from the highest order unit passing a selected one of said highest order intermediate signals to said output.
Claim 7
Dependent Claim
30 words
The circuit of claim 5 wherein said control signal providing means further comprises feedback means connected to said output to compensate for variations in the frequency of the input signal.
Claim 8
Dependent Claim
30 words
The circuit of claim 6 wherein said feedback means comprises a phase locked loop including a phase detector, a voltage controlled oscillator and a digital divider circuit connected in series.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-01 | 1986-05-03 | 1986-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-01 | 1990-05-03 | 1990-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-01 | 1994-05-03 | 1994-11-02 | $7700.00 | Window Closed / Lapsed |