Device for processing telephone signals, including a processor and a preprocessor sharing a common memory

Claim 2

In a telecommunication system wherein a multiplicity of circuit points are partly monitored by sensors and partly controlled by drivers, including a processor for handling incoming signals from said sensors and causing the emission of outgoing signals to said drivers, the combination therewith of: a preprocessor with input connections from said sensors and output connections to said drivers; a common memory available to said processor and to said preprocessor; and a bus interlinking said processor, said preprocessor and said common memory; said preprocessor comprising a microprogrammer responsive to an instruction from said processor, communicated via said bus, for carrying out a sequence of operations involving a seizure of said bus by said preprocessor for the duration of said sequence, a scanning of consecutive circuit points on the basis of address information supplied by said common memory, reception of incoming signals and emission of outgoing signals relating to points being scanned, and an evaluation of said incoming signals, said preprocessor further comprising logical circuitry for performing said evaluation by an exchange of data with said common memory through said bus, said logical circuitry including a read-only memory jointly addressable by a current-state signal from a given circuit point and a previous-state signal from said common memory for supplying integration codes determining the recognition of a definite change of state to be communicated to said processor, said microprogrammer including a microprogram memory stepped by a sequencer and a logic network inserted between said microprogram memory and said sequencer for commanding the performance of lower-priority tasks after the scanning of said circuit points and prior to release of the bus by said preprocessor.

Claim 3

The combination defined in claim 1 wherein said logical circuitry further includes a working memory for storing an initial address received from said common memory at the beginning of said sequence, and arithmetic means controlled by said microprogrammer for modifying said initial address on the basis of signals identifying the scanned circuit points.

Claim 4

In a telecommunication system wherein a multiplicity of circuit points are partly monitored by sensors and partly controlled by drivers, including a processor for handling incoming signals from said sensors and causing the emission of outgoing signals to said drivers, the combination therewith of: a preprocessor with input connections from said sensors and output connections to said drivers; a common memory available to said processor and to said preprocessor; and a bus interlinking said processor, said preprocessor and said common memory; said preprocessor comprising: (a) a microprogrammer responsive to an instruction from said processor, communicated via said bus, for carrying out a sequence of operations involving a seizure of said bus by said preprocessor for the duration of said sequence, a scanning of consecutive circuit points on the basis of address information supplied by said common memory, reception of incoming signals and emission of outgoing signals relating to points being scanned, and an evaluation of said incoming signals, (b) logical circuitry for performing said evaluation by an exchange of data with said common memory through said bus, said logical circuitry including a read-only memory jointly addressable by a current-state signal from a given circuit point and a previous-state signal from said common memory for supplying integration codes determining the recognition of a definite change of state to be communicated to said processor, said logical circuitry further including a working memory for storing an initial address received from said common memory at the beginning of said sequence, and arithmetic means controlled by said microprogrammer for modifying said initial address on the basis of signals identifying the scanned circuit points, and (c) input and output registers for the temporary storage of incoming and outgoing signals, respectively, other registers for the temporary storage of data arriving from and leaving for said common memory via said bus, and a further register inserted between said arithmetic means and said bus for reading out modified addresses throughout the seizure of said bus by said preprocessor.

Claim 5

In a telecommunication system wherein a multiplicity of circuit points are partly monitored by sensors and partly controlled by drivers, including a processor for handling incoming signals from said sensors and causing the emission of outgoing signals to said drivers, the combination therewith of: a preprocessor with input connections from said sensors and output connections to said drivers; a common memory available to said processor and to said preprocessor; and a bus interlinking said processor, said preprocessor and said common memory; said preprocessor comprising: (a) a microprogrammer responsive to an instruction from said processor, communicated via said bus, for carrying out a sequence of operations involving a seizure of said bus by said preprocessor for the duration of said sequence, a scanning of consecutive circuit points on the basis of address information supplied by said common memory, reception of incoming signals and emission of outgoing signals relating to points being scanned, and an evaluation of said incoming signals, (b) logical circuitry for performing said evaluation by an exchange of data with said common memory through said bus, said logical circuitry including a read-only memory jointly addressable by a current-state signal from a given circuit point and a previous-state signal from said common memory for supplying integration codes determining the recognition of a definite change of state to be communicated to said processor, said logical circuitry further including a working memory for storing an initial address received from said common memory at the beginning of said sequence, and arithmetic means controlled by said microprogrammer for modifying said initial address on the basis of signals identifying the scanned circuit points, and (c) input and output registers for the temporary storage of incoming and outgoing signals, respectively, other registers for the temporary storage of data arriving from and leaving for said common memory via said bus, and a further register inserted between said arithmetic means and said bus for reading out modified addresses throughout the seizure of said bus by said preprocessor.

Claim 6

The combination defined in claim 3, wherein said microprogrammer includes a microprogram memory stepped by a sequencer and a logic network inserted between said microprogram memory and said sequencer for commanding the performance of lower-priority tasks after the scanning of said circuit points and prior to release of the bus by said preprocessor.

Claim 7

The combination defined in claim 3 wherein said read-only memory has cells containing sample codes for the generation of outgoing signals, said cells being jointly addressable by a predetermined incoming signal from driver-controlled circuit points and data bits stored in areas of said common memory respectively allocated to such circuit points.